FAN5234MTCX Fairchild Semiconductor, FAN5234MTCX Datasheet - Page 9

• Manufacturer Part Number: FAN5234MTCX
• Description: IC CTRLR PWM/PFM MOBILE 16TSSOP
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5234MTCX

• Applications: Controller, Mobile PCs
• Voltage - Input: 2 ~ 24 V
• Number Of Outputs: 1
• Voltage - Output: 0.9 ~ 5.5 V
• Operating Temperature: -10°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Output Voltage: 0.9 V to 15 V
• Input Voltage: 2 V to 24 V
• Switching Frequency: 300 KHz to 600 KHz
• Operating Temperature Range: - 10 C to + 85 C
• Mounting Style: SMD/SMT
• Duty Cycle (max): 87 %
• Isolated/non-isolated: Non Isolated
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
More accurate sensing can be achieved by using a
resistor (R1) instead of the R
in Figure 5. This approach causes higher losses, but
yields greater accuracy in both V
low value (e.g. 10mΩ) resistor.
Current limit (I
inductor current to rise in response to an output load
transient. Typically, a factor of 1.2 is sufficient. Since
I
the inductor ripple current (use 25%). For example, in
Figure 1 the target for I
I
Duty Cycle Clamp
During severe load increase, the error amplifier output
can go to its upper limit, pushing a duty cycle to almost
100% for a significant amount of time. This could cause
a large increase of the inductor current and lead to a
long recovery from a transient over-current condition or
even to a failure at high input voltages. To prevent this,
the output of the error amplifier is clamped to a fixed
value after two clock cycles if severe output voltage
excursion is detected, limiting maximum duty cycle to:
This is designed to not interfere with normal PWM
operation. When FPWM is grounded, the duty cycle
clamp is disabled and the maximum duty cycle is 87%.
Gate Driver
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive
signals, providing necessary amplification, level shifting,
and shoot-through protection. It also has functions that
help optimize the IC performance over a wide range of
DC
LIMIT
LIMIT
C
MAX
S S
is a peak current cut-off value, multiply I
> 1.2 x 1.25 x 1.6 x 3.5A
V SE N
=
V
V
OUT
S S
IN
+
⎛
⎜
⎜
⎝
V
LIMIT
2
IN
4 .
⎞
⎟
⎟
⎠
) should be set high enough to allow
3 0 0 K
LIMIT
Reference
Soft-Start
would be:
DS(ON)
1 .5 M
and
≈
8.5A
DROOP
0 .1 7 p f
of the FET, as shown
Figure 6. Current Limit / Summing Circuits
1 7 pf
ILIM det.
and I
C O M P
P W M
TO
LIMIT
4 .1 4 K
LOAD(MAX)
. R1 is a
(6)
(7)
by
2 .5 V
9
operating conditions. Since MOSFET switching time
can vary dramatically from type to type and with the
input voltage, the gate control logic provides adaptive
dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET
drive is not turned on until the gate-to-source voltage of
the upper MOSFET has decreased to less than
approximately 1V. Similarly, the upper MOSFET is not
turned on until the gate-to-source voltage of the lower
MOSFET has decreased to less than approximately 1V.
This allows a wide variety of upper and lower MOSFETs
to be used without concern for simultaneous conduction
or shoot-through.
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the
adaptive dead-time circuit to work properly. Any delay
along that path subtracts from the delay generated by the
adaptive dead-time circuit and shoot-through may occur.
Frequency Loop Compensation
Due to the implemented current-mode control, the
modulator has a single-pole response with -1 slope at
frequency determined by load. Therefore:
where R
For this type of modulator, type-2 compensation circuit
is usually sufficient. To reduce the number of external
components and simplify the design task, the PWM
controller has an internally compensated error amplifier.
Figure 7 shows a type two amplifier, its response, and
the responses of a current mode modulator and the
converter. The type-2 amplifier, in addition to the pole at
the origin, has a zero-pole pair that causes a flat gain
region at frequencies between the zero and the pole.
f
PO
=
ISNS
2
I2 =
π
O
R
1
is load resistance and C
V to I
O
C
O
0 .9 V
S / H
ISNS
IL IM *11
ILIM
in+
in-
O
L D RV
P GN D
is load capacitance.
ISN S
ILIM
R
R
www.fairchildsemi.com
SE NSE
ILIM
(8)