FAN5234QSCX Fairchild Semiconductor, FAN5234QSCX Datasheet - Page 10

• Manufacturer Part Number: FAN5234QSCX
• Description: IC CTRLR PWM/PFM MOBILE 16QSOP
• Manufacturer: Fairchild Semiconductor

Specifications of FAN5234QSCX

• Applications: Controller, Mobile PCs
• Voltage - Input: 2 ~ 24 V
• Number Of Outputs: 1
• Voltage - Output: 0.9 ~ 5.5 V
• Operating Temperature: -10°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Operating Temperature Range: - 10 C to + 150 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FAN5234QSCXTR; FAN5234QSCX_NL; FAN5234QSCX_NLTR; FAN5234QSCX_NLTR

© 2004 Fairchild Semiconductor Corporation
FAN5234 • Rev. 2.0.0
This region is also associated with phase “bump” or
reduced phase shift. The amount of phase shift
reduction depends the width of the region of flat gain
and has a maximum value of 90°. To further simplify the
converter compensation, the modulator gain is kept
independent of the input voltage variation by providing
feed-forward of V
The zero frequency, the amplifier high-frequency gain,
and the modulator gain are chosen to satisfy most
typical applications. The crossover frequency appears
at the point where the modulator attenuation equals the
amplifier high-frequency gain. The system designer
must specify the output filter capacitors to position the
load main pole somewhere within one decade lower
than the amplifier zero frequency. With this type of
compensation, plenty of phase margin is achieved due
to zero-pole pair phase “boost.”
Conditional stability may occur only when the main load
pole is positioned too much to the left side on the
frequency
capacitance. In this case, the ESR zero placed within
the 10kHz to 50kHz range gives some additional phase
boost. There is an opposite trend in mobile applications
to keep the output capacitor as small as possible.
Protections
The converter output is monitored and protected
against extreme overload, short circuit, over-voltage,
and under-voltage conditions.
A sustained overload on an output sets the PGOOD pin
LOW and latches off the chip. Operation is restored by
cycling the V
If V
chip shuts down immediately.
f
f
P
Z
18
14
=
=
0
OUT
2
2
Modulator
V
π
π
IN
R
R
drops below the under-voltage threshold, the
1
1
2
2
C
C
1
2
axis
R1
CC
f
REF
=
P0
=
Figure 7. Compensation
6
voltage or by toggling the EN pin.
600
kHz
IN
due
to the oscillator ramp.
kHz
R2
C2
C1
to
f
EA Out
Z
excessive
output
f
P
(10)
(9)
filter
10
Over-Current Sensing
If the circuit's current-limit signal (“I
is HIGH at the beginning of a clock cycle, a pulse-
skipping circuit is activated and HDRV is inhibited. The
circuit continues to pulse skip in this manner for the
next eight clock cycles. If at any time from the ninth to
the sixteenth clock cycle, the I
the over-current protection latch is set, disabling the
chip. If I
normal operation is restored and the over-current circuit
resets itself.
1
2
3
Over-Voltage / Under-Voltage Protection
Should the V
due to an upper MOSFET failure or for other reasons,
the over-voltage protection comparator forces LDRV
HIGH. This action actively pulls down the output voltage
and, in the event of the upper MOSFET failure,
eventually blows the battery fuse. As soon as the output
voltage drops below the threshold, the OVP comparator
is disengaged.
This OVP scheme provides a ‘soft’ crowbar function to
tackle severe load transients and does not invert the
output voltage when activated — a common problem for
latched OVP schemes.
Similarly, if an output short-circuit or severe load
transient causes the output to droop to less than 75% of
its regulation set point, the regulator shuts down.
Over-Temperature Protection
The chip incorporates an over-temperature protection
circuit that shuts the chip down when a die temperature
reaches 150°C. Normal operation is restored at die
temperature below 125°C with internal power on reset
asserted, resulting in a full soft-start cycle.
CH1 5.0V
CH3 2.0AW
Figure 8. Over-Current Protection Waveforms
I L
LIM
det does not occur between cycles 9 and 16,
SEN
PGOOD
V
OUT
voltage exceed 120% of V
CH2 100mV
8 CLK
LIM
det is again reached,
LIM
det” in Figure 6)
www.fairchildsemi.com
REF
M 10.0s
(0.9V)