FDMF8704V Fairchild Semiconductor, FDMF8704V Datasheet - Page 2

IC MOD DVR/FET W/VREG 56MLP 8X8

FDMF8704V

Manufacturer Part Number
FDMF8704V
Description
IC MOD DVR/FET W/VREG 56MLP 8X8
Manufacturer
Fairchild Semiconductor
Type
Step-Down (Buck)r
Datasheet

Specifications of FDMF8704V

Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
0.8 ~ 3.2 V
Current - Output
32A
Frequency - Switching
1MHz
Voltage - Input
7 ~ 20 V
Operating Temperature
-55°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
56-MLP
Power - Output
10W
Supply Voltage (min)
4.5 V
Supply Current
50 mA
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Number Of Drivers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
FDMF8704VTR
FDMF8704V Rev. G
Pin Configuration
Pin Description
8, 9, 11-20, B
21, 40-50, C
1, 6, 51, A
22-38
7, 53
Pin
10
39
52
54
55
56
2
3
4
5
TEST PAD 1
TEST PAD 2
REGOUT
REGFB
Name
CGND
VSWH
PGND
HSEN
BOOT
VAUX
PWM
VCIN
DISB
VIN
NC
REGOUT
REGFB
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
CGND
PWM
DISB
NC
IC Ground. Ground return for driver IC.
High Side FET Enable. Must be connected to BOOT pin.
Auxiliary Power for 5V regulator Op-Amp.
IC Supply. +5V chip bias power. Bypass with a 1µF ceramic capacitor.
Bootstrap Supply Input. Provides voltage supply to high-side MOSFET driver. Connect to
bootstrap capacitor.
No Connect.
Switch Node Input. SW Provides return for high-side bootstrapped driver and acts as a
sense point for the adaptive shoot-thru protection.
Power Input. Output stage supply voltage.
For manufacturing test only. HDRV pin. This pin must be floated. Must not be connected to
any pin.
Power Ground. Output stage ground. Source pin of low side MOSFET(s).
For manufacturing test only. LDRV pin. This pin must be floated. Must not be connected to
any pin.
Regulator Driver Output. An external NPN transistor is used to generate the 5V output
voltage with internal controller.
Regulation Sense Input. The internal resistor divider will set this voltage to be regulated at
5V.
Output Disable. When low, this pin disable FET switching (HDRV and LDRV are held low).
PWM Signal Input. This pin accepts a logic-level PWM signal from the controller.
56
43
Figure 2. MLP 8x8 56L Bottom View
42
1
(CGND)
A
(VSWH)
2
C
(VIN)
B
14
29
Function
15
28
VIN
VIN
VIN
VIN
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
PGND
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