LTC3716EG Linear Technology, LTC3716EG Datasheet - Page 19

• Manufacturer Part Number: LTC3716EG
• Description: IC SW REG STP-DN 5BIT SYNC36SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC3716EG

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 ~ 1.75 V
• Current - Output: 35mA
• Frequency - Switching: 120kHz ~ 310kHz
• Voltage - Input: 4 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIO S I FOR ATIO
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to latch off the
controllers when an overcurrent condition is detected. The
RUN/SS capacitor, C
current of both controllers. After the controllers have been
started and been given adequate time to charge up the
output capacitors and provide full load current, the RUN/
SS capacitor is used for a short-circuit timer. If the output
voltage falls to less than 70% of its nominal value after C
reaches 4.1V, C
that the output is in an overcurrent condition. If the
condition lasts for a long enough period as determined by
the size of the C
RUN/SS pin voltage is recycled. If the overload occurs
during start-up, the time can be approximated by:
If the overload occurs after start-up, the voltage on C
continue charging and will provide additional time before
latching off:
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor, R
shown in Figure 6. This resistance shortens the soft-start
period and prevents the discharge of the RUN/SS capaci-
tor during a severe overcurrent and/or short-circuit con-
dition. When deriving the 5 A current from V
figure, current latchoff is always defeated. The diode
connecting this pull-up resistor to INTV
eliminates any extra supply current during shutdown
while eliminating the INTV
controller start-up.
Why should you defeat current latchoff? During the
prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is com-
plete whether to rely solely on foldback current limiting or
to enable the latchoff feature by removing the pull-up
resistor.
t
t
LO1
LO2
(C
(C
SS
SS
• 0.6V)/(1.2 A) = 5 • 10
• 3V)/(1.2 A) = 2.5 • 10
SS
SS
, the controller will be shut down until the
begins discharging on the assumption
U
SS
, is used initially to limit the inrush
U
CC
SS
loading from preventing
, to the RUN/SS pin as
W
5
6
CC
(C
(C
, as in Figure 6,
SS
SS
)
)
IN
U
as in the
SS
will
SS
The value of the soft-start capacitor C
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
The minimum recommended soft-start capacitor of C
0.1 F will be sufficient for most applications.
Phase-Locked Loop and Frequency Synchronization
The LTC3716 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is 50% around the
center frequency f
of 1.2V corresponds to a frequency of approximately
220kHz. The nominal operating frequency range of the
LTC3716 is 140kHz to 310kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, f
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 7.
C
PLLIN
SS
f
H
EXTERNAL
= f
> (C
OSC
H
Figure 7. Phase-Locked Loop Block Diagram
, is equal to the capture range, f
C
OUT
= 0.5 f
50k
)(V
O
OUT
FREQUENCY
. A voltage applied to the PLLFLTR pin
DETECTOR
DETECTOR
DIGITAL
PHASE/
PHASE
O
)(10
(150kHz-300kHz)
-4
)(R
SENSE
2.4V
)
SS
may need to be
LTC3716
C:
PLLFLTR
R
10k
LP
3716 F07
19
OSC
C
LP
SS
=