MT8VDDT6464AG-335F3 Micron Technology Inc, MT8VDDT6464AG-335F3 Datasheet - Page 10

• Manufacturer Part Number: MT8VDDT6464AG-335F3
• Description: MODULE DDR SDRAM 512MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6464AG-335F3

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6:
NOTE:
Table 7:
pdf: 09005aef80867ab3, source: 09005aef80867a99
DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
1. For a burst length of two, A1–Ai select the two-
2. For a burst length of four, A2–Ai select the four-
3. For a burst length of eight, A3–Ai select the eight-
4. Whenever a boundary of the block is reached
5. i = 9 (128MB, 256MB)
LENGTH
BURST
data-element block; A0 selects the first access
within the block.
data-element block; A0–A1 select the first access
within the block.
data-element block; A0–A2 select the first access
within the block.
within a given sequence above, the following
access wraps within the block.
i = 9, 11 (512MB)
SPEED
2
4
8
-26A
-335
-262
-265
A2 A1 A0
STARTING
ADDRESS
0
0
0
0
1
1
1
1
COLUMN
Burst Definition Table
CAS Latency (CL) Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 100
A0
0 0-1
1 1-0
0 0-1-2-3
1 1-2-3-0
0 2-3-0-1
1 3-0-1-2
0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
CLOCK FREQUENCY (MHZ)
CL = 2
ALLOWABLE OPERATING
ORDER OF ACCESSES WITHIN
SEQUENTIAL
TYPE =
A BURST
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
75 ≤ f ≤ 167
75 ≤ f ≤ 133
75 ≤ f ≤ 133
75 ≤ f ≤ 133
INTERLEAVED
CL = 2.5
TYPE =
10
Operating Mode
MODE REGISTER SET command with bits A7
(128MB), or A7
and bits A0
initiated by issuing a MODE REGISTER SET command
with bits A7 and A9
(256MB, 512MB) each set to zero, bit A8 set to one, and
bits A0
required by the Micron device, JEDEC specifications
recommend when a LOAD MODE REGISTER com-
mand is issued to reset the DLL, it should always be
followed by a LOAD MODE REGISTER command to
select normal operating mode.
A12, are reserved for future use and/or test modes.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Extended Mode Register
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 7, Extended Mode Register
Definition Diagram, on page 11. The extended mode
register is programmed via the LOAD MODE REGIS-
COMMAND
COMMAND
128MB, 256MB, 512MB (x64, SR)
The normal operating mode is selected by issuing a
All other combinations of values for A7
The extended mode register controls functions
DQS
DQS
CK#
CK#
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 6: CAS Latency Diagram
CK
CK
184-PIN DDR SDRAM UDIMM
–
A6 set to the desired values. Although not
–
A6 set to the desired values. A DLL reset is
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
–
A12 (256MB, 512MB) each set to zero,
–
A11 (128MB), or A7 and A9
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
T1
T1
T2
NOP
NOP
T2
©2004 Micron Technology. Inc.
T2n
T2n
DON’T CARE
–
A11, or A7
T3
NOP
NOP
T3
–
–
T3n
T3n
A11
A12
–