MT8VDDT6464AG-335F3 Micron Technology Inc, MT8VDDT6464AG-335F3 Datasheet - Page 20

• Manufacturer Part Number: MT8VDDT6464AG-335F3
• Description: MODULE DDR SDRAM 512MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6464AG-335F3

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pdf: 09005aef80867ab3, source: 09005aef80867a99
DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
refreshing or posting by the DRAM controller
greater than eight refresh cycles is not allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain. Figure 8, Derating Data Valid Window,
shows derating curves for duty cycles ranging
between 50/50 and 45/55.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
the input must:
a. Sustain a constant slew rate from the current
t
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
QH =
AC level through to the target AC level, V
or V
t
50/50
IH
HP -
3.750
2.500
(
AC
t
).
QHS). The data valid window derates
N/A
49.5/50.5
3.700
-335 @
-262/-26A/-265 @
-262/-26A/-265 @
2.463
t
HP (
t
CK = 6ns
t
Figure 8: Derating Data Valid Window
3.650
49/51
CK/2),
2.425
t
t
CK = 10ns
CK = 7.5ns
t
RFC [MIN]) else
t
DQSQ, and
48.5/52.5
3.600
2.388
IL
3.550
48/52
(
t
(
t
QH
AC
QH -
2.350
)
Clock Duty Cycle
20
t
DQSQ)
47.5/53.5
3.500
26. CK and CK# input slew rate must be ≥ 1V/ns (≤2V/
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30.
128MB, 256MB, 512MB (x64, SR)
2.313
ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4 V/ns, functionality is uncer-
tain.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
t
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
b. Reach at least the target AC level.
c. After the AC target level is reached, continue
DH for each 100mv/ns reduction in slew rate. If
HP min is the lesser of
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
184-PIN DDR SDRAM UDIMM
to maintain at least the target DC level, V
or V
47/53
3.450
must not vary more than 4 percent if CKE is
2.275
IH
(
DC
46.5/54.5
).
3.400
2.238
3.350
46/54
2.200
t
CL minimum and
45.5/55.5
3.300
©2004 Micron Technology. Inc.
2.163
t
3.250
45/55
DS and
IL
2.125
(
DC
t
CH
)