MT8VDDT6464AG-335F3 Micron Technology Inc, MT8VDDT6464AG-335F3 Datasheet - Page 19

• Manufacturer Part Number: MT8VDDT6464AG-335F3
• Description: MODULE DDR SDRAM 512MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6464AG-335F3

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Notes
pdf: 09005aef80867ab3, source: 09005aef80867a99
DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
10. I
11. This parameter is sampled. V
1. All voltages referenced to V
2. Tests for AC timing, Idd, and electrical AC and DC
3. Outputs measured with equivalent load:
4. AC timing and I
5. The AC and DC input level specifications are as
6. V
7. V
8. I
9. Enables on-chip refresh and address counters.
characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.
swing of up to 1.5V in the test environment, but
input timing is still referenced to V
crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V
and V
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V
DC value. From V
for DC error and an additional ±25mV for AC
noise, measured at the nearest V
itor.
system supply for signal termination resistors, is
expected to be set equal to V
variations in the DC level of V
rates. Specified values are obtained with mini-
mum cycle time at CL = 2 for -26A and CL = 2.5 for
-335 and -265 with the outputs open.
properly initialized, and is averaged at the defined
cycle rate.
V
25°C, V
DD
DD
REF
TT
DD
Q = +2.5V ±0.2V, V
is not applied directly to the device. V
is dependent on output loading and cycle
specifications are tested after the device is
is expected to equal VddQ/2 of the transmit-
IH
OUT
(
AC
).
(
REF
DC
Output
(V
OUT
) = V
may not exceed ±2 percent of the
)
DD
DD
DD
V
Q/2, V
tests may use a V
TT
Q/2, V
REF
50
30pF
Reference
Point
Ω
= Vss, f = 100 MHz, T
SS
REF
OUT
.
REF
REF
DD
is allowed ±25mV
REF
.
, and must track
(peak to peak) =
= +2.5V ±0.2V,
bypass capac-
REF
(or to the
IL
-to-V
TT
IL
(
is a
AC
A
IH
=
)
19
12. For slew rates < 1 V/ns and ≥ 0.5 Vns. If slew rate is
13. The CK/CK# input reference level (for timing ref-
14. Inputs are not recognized as valid until V
15. The output timing reference level, as measured at the
16.
17. The intent of the Don’t Care state after completion
18. This is not a device limit. The device will operate
19. It is recommended that DQS be valid (HIGH or
20. MIN (
21. The refresh period 64ms. This equates to an aver-
128MB, 256MB, 512MB (x64, SR)
0.2V. DM input is grouped with I/O pins, reflecting
the fact that they are matched in loading.
less than 0.5 V/ns, timing must be derated:
an additional 50ps per each 100 mV/ns reduction
in slew rate from 500 mV/ns, while
fected. If slew rate exceeds 4.5V/ns, functionality
is uncertain.
erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V
lizes. Exception: during the period before Vref sta-
bilizes, CKE ≤ 0.3 x V
timing reference point indicated in Note 3, is V
t
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
of the postamble is the DQS-driven signal should
either be high, low, or high-Z and that any signal
transition within the input switching region must
follow valid input requirements. That is, if DQS
transitions high (above V
not transition low (below V
(MIN).
with a negative value, but system performance
could be degraded due to bus turnaround.
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on
smallest multiple of
absolute value for the respective parameter.
(MAX) for I
ple of
value for
age refresh rate of 15.625µs (128MB), or 7.8125µs
(256MB, 512MB). However, an AUTO REFRESH
command must be asserted at least once every
140.6µs (128MB) or 70.3µs (256MB, 512MB); burst
HZ and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
t
RC or
t
CK that meets the maximum absolute
t
t
LZ transitions occur in the same access
RAS.
DD
t
RFC) for I
t
measurements is the largest multi-
DQSS.
DD
t
CK that meets the minimum
REF
Q is recognized as LOW.
DD
IHDC
.
IHDC
measurements is the
(MIN) then it must
) prior to
©2004 Micron Technology. Inc.
t
IH is unaf-
REF
t
t
DQSH
IS has
stabi-
TT
t
RAS
.