MT18VDDF12872HY-335D1 Micron Technology Inc, MT18VDDF12872HY-335D1 Datasheet
MT18VDDF12872HY-335D1
Specifications of MT18VDDF12872HY-335D1
Related parts for MT18VDDF12872HY-335D1
MT18VDDF12872HY-335D1 Summary of contents
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SMALL-OUTLINE DDR SDRAM DIMM Features • 200-pin, small-outline, dual in-line memory module (SODIMM) • Fast data transfer rates: PC2100 and PC2700 • Utilizes 266 MT/s or 333 MT/s DDR SDRAM components • ECC, 1-bit error detection and correction • 512MB ...
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... MT18VDDF6472HG-265__ MT18VDDF6472HY-265__ MT18VDDF12872HG-335__ MT18VDDF12872HY-335__ MT18VDDF12872HG-262__ MT18VDDF12872HY-262__ MT18VDDF12872HG-26A__ MT18VDDF12872HY-26A__ MT18VDDF12872HG-265__ MT18VDDF12872HY-265__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDF6472HG-265A1. 09005aef80e487d7 DDF18C64_128x72HG_A.fm - Rev. A 10/03 EN CONFIGURATION TRANSFER 512MB 64 Meg x 72 ...
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Table 3: Pin Assignment (200-Pin SODIMM Front) PIN PIN PIN SYMBOL SYMBOL 101 REF DQ19 103 SS 5 DQ0 55 DQ24 105 7 DQ1 57 V 107 DQ25 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS 118, 119, 120 CAS#,RAS# 35, 37, 158, 160 CK0, CK0# CK1, CK1# 95, 96 CKE0, CKE1 ...
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... No Connect: These pins should be left unconnected. DNU — Do Not Use: These pins are not connected on this module, but are assigned pins on other modules in this product family. 5 512MB, 1GB (x72, ECC, DR) 200-PIN DDR SODIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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S1# S0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 ...
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... General Description The MT18VDDF6472H and MT18VDDF12872H are high-speed CMOS, dynamic random-access, 512MB and 1GB memory modules organized in a x72 configu- ration. These modules use internally configured quad- bank DRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double ...
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Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being program- mable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode regis- ter (BA0/ ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 512MB DD Notes: 1–5, 8, 10, 12, 47; DDR SDRAM devices only; notes appear on pages 17–20; 0°C £ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 13: I Specifications and Conditions – 1GB DD Notes: 1–5, 8, 10, 12, 47; DDR SDRAM devices only; notes appear on pages 17–20; 0°C £ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 14: Capacitance Note: 11; notes appear notes appear on pages 17–20 PARAMETER Input/Output Capacitance: DQ, DQS,DM Input Capacitance: Command and Address, RAS#, CAS#, WE# Input Capacitance: CK, CK#, Input Capacitance: CKE, S# Table 15: DDR SDRAM Component Electrical Characteristics ...
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Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 12–15, 29, 40; notes appear on pages 17–20; 0°C £ CHARACTERISTICS PARAMETER Address and control input setup time (slow slew rate) Address and ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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The refresh period 64ms. This equates to an aver- age refresh rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh ...
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HP min is the lesser of CL minimum and minimum actually applied to the device CK and CK# inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not t allowed to be issued ...
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Random addressing changing and 50 percent of data changing at every transfer. 42. Random addressing changing and 100 percent of data changing at every transfer. 43. CKE must be active (high) during the entire time a refresh command is ...
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... The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules. Case temperatures charted represent worst-case component locations on modules installed in the internal slots of the system. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data Validity, and Figure ...
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Table 16: EEPROM Device Select Code Most significant bit (b7) is sent first. SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 17: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read Sequential ...
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Table 18: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 20: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 26 BYTE DESCRIPTION 0 Number of Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 ...
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... The value of RAS used for -262/-26A/-265 modules is calculated from 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met ...
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Figure 15: 200-PIN SODIMM Dimensions 0.079 (2.00 (2X) 0.071 (1.80) U5 (2X) 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (.99) TYP PIN 1 U11 U15 PIN 200 NOTE: All dimensions are in inches (millimeters); Data Sheet Designation Released ...