MT18VDDF12872HY-335D1 Micron Technology Inc, MT18VDDF12872HY-335D1 Datasheet - Page 15

• Manufacturer Part Number: MT18VDDF12872HY-335D1
• Description: MODULE SDRAM DDR 512MB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872HY-335D1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.53A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14: Capacitance
Note: 11; notes appear notes appear on pages 17–20
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Notes: 1–5, 12–15, 29, 40; notes appear on pages 17–20; 0°C £ T
09005aef80e487d7
DDF18C64_128x72HG_A.fm - Rev. A 10/03 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to
DQS
DQ and DM input setup time relative to
DQS
DQ and DM input pulse width (for each
input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per
group, per access
Write command to first DQS latching
transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold
time
Half clock period
Data-out high-impedance window from
CK/CK#
Data-out low-impedance window from CK/
CK#
Address and control input hold time (fast
slew rate)
Address and control input setup time (fast
slew rate)
Address and control input hold time (slow
slew rate)
PARAMETER
Input/Output Capacitance: DQ, DQS,DM
Input Capacitance: Command and Address, RAS#, CAS#, WE#
Input Capacitance: CK, CK#,
Input Capacitance: CKE, S#
Operating Conditions
CL=2.5
CL=2
SYMBOL MIN
t
t
CK (2.5)
t
t
t
DQSCK
t
t
t
CK (2)
DQSH
DQSQ
t
DIPW
DQSL
DQSS
t
t
t
t
DSH
t
t
t
t
t
t
DSS
t
t
DH
AC
CH
HP
HZ
IH
IH
DS
CL
LZ
IS
F
F
S
-0.70
-0.60
-0.70
0.45
0.45
0.45
0.45
1.75
0.35
0.35
0.75
0.20
0.20
0.75
0.75
7.5
0.8
6
t
CH,
15
-335
A
t
MAX
+0.70
+0.60
+0.70
CL
0.55
0.55
1.25
£ +65°C; V
0.4
13
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
-0.75
-0.75
-0.75
MIN
0.45
0.45
1.75
0.35
0.35
0.75
0.20
0.20
0.90
0.90
7.5
7.5
0.5
0.5
512MB, 1GB (x72, ECC, DR)
DD
1
t
CH,
= V
SYMBOL
-262
C
DD
t
C
C
C
CL
MAX
+0.75
+0.75
+0.75
IO
200-PIN DDR SODIMM
I1
I2
I3
0.55
0.55
1.25
0.5
Q = +2.5V ±0.2V
13
13
MIN MAX
0.45
0.45
0.35
0.35
0.75
0.20
0.20
-0.8
-0.8
-0.8
0.6
0.6
1.1
1.1
1.1
10
8
2
t
CH,
-202
MIN
13.5
t
+0.8
0.55
0.55
+0.8
1.25
+0.8
CL
27
0.6
13
13
7
9
MAX
UNITS
©2003 Micron Technology, Inc.
45
15
22
9
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
UNITS
NOTES
40, 45
40, 45
23, 27
23, 27
22, 23
16, 37
16, 38
pF
pF
pF
pF
26
26
27
12
12
12
7