MA180023 Microchip Technology, MA180023 Datasheet - Page 133

• Manufacturer Part Number: MA180023
• Description: MODULE PLUG-IN PIC18F46J11 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA180023

• Accessory Type: Plug-In Module (PIM) - PIC18F46J11
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: PIC18
• Supported Devices: Stand-alone Or W/ HPC(DM183022) Or PIC18(DM183032)
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18FxxJxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: HPC Explorer Board (DM183022) or PIC18 Explorer Board (DM183032)
• For Use With: DM183032 - BOARD EXPLORER PICDEM PIC18DM183022 - BOARD DEMO PIC18FXX22 64/80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 9-5:
© 2009 Microchip Technology Inc.
RB0/AN12/
INT0/RP3
RB1/AN10/
RTCC/RP4
RB2/AN8/
CTEDG1/
REFO/RP5
RB3/AN9/
CTEDG2/
PMA2/RP6
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
Pin
2:
3:
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog
inputs by default when PBADEN is set and digital inputs when PBADEN is cleared.
All other pin functions are disabled when ICSP™ or ICD are enabled.
This bit is not available on 28-pin devices.
PORTB I/O SUMMARY
Function
CTEDG1
CTEDG2
PMA2
RTCC
REFO
AN12
AN10
INT0
RB0
RP3
RB1
RP4
RB2
AN8
RP5
RB3
AN9
RP6
(3)
Setting
TRIS
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
1
0
1
0
I/O
O
O
O
O
O
O
O
O
O
O
O
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
TTL
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
PORTB<0> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
LATB<0> data output; not affected by analog input.
A/D input channel 12.
External interrupt 0 input.
Remappable peripheral pin 3 input.
Remappable peripheral pin 3 output.
PORTB<1> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
LATB<1> data output; not affected by analog input.
A/D input channel 10.
Asynchronous serial transmit data output (USART module).
Remappable peripheral pin 4 input.
Remappable peripheral pin 4 output.
PORTB<2> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
LATB<2> data output; not affected by analog input.
A/D input channel 8.
CTMU Edge 1 input.
Reference output clock.
Remappable peripheral pin 5 input.
Remappable peripheral pin 5 output.
LATB<3> data output; not affected by analog input.
PORTB<3> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
A/D input channel 9.
CTMU edge 2 input.
Parallel Master Port address.
Remappable peripheral pin 6 input.
Remappable peripheral pin 6 output.
PIC18F46J11 FAMILY
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Description
DS39932C-page 133
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