DK-DEV-2AGX260N Altera, DK-DEV-2AGX260N Datasheet - Page 45

• Manufacturer Part Number: DK-DEV-2AGX260N
• Description: KIT DEV FPGA 2AGX260 W/6.375G TX
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX260N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2696

Chapter 2: Board Components
Components and Interfaces
Table 2–37. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
© July 2010 Altera Corporation
Reference
J1.102
J1.103
J1.104
J1.107
J1.108
J1.109
J1.110
J1.113
J1.114
J1.115
J1.116
J1.119
J1.120
J1.121
J1.122
J1.125
J1.126
J1.127
J1.128
J1.131
J1.132
J1.133
J1.134
J1.137
J1.138
J1.139
J1.140
J1.143
J1.144
J1.145
J1.146
J1.149
J1.150
J1.151
J1.152
J1.155
J1.156
J1.157
Board
Dedicated CMOS I/O bit 41
Dedicated CMOS I/O bit 42
Dedicated CMOS I/O bit 43
Dedicated CMOS I/O bit 44
Dedicated CMOS I/O bit 45
Dedicated CMOS I/O bit 46
Dedicated CMOS I/O bit 47
Dedicated CMOS I/O bit 48
Dedicated CMOS I/O bit 49
Dedicated CMOS I/O bit 50
Dedicated CMOS I/O bit 51
Dedicated CMOS I/O bit 52
Dedicated CMOS I/O bit 53
Dedicated CMOS I/O bit 54
Dedicated CMOS I/O bit 55
Dedicated CMOS I/O bit 56
Dedicated CMOS I/O bit 57
Dedicated CMOS I/O bit 58
Dedicated CMOS I/O bit 59
Dedicated CMOS I/O bit 60
Dedicated CMOS I/O bit 61
Dedicated CMOS I/O bit 62
Dedicated CMOS I/O bit 63
Dedicated CMOS I/O bit 64
Dedicated CMOS I/O bit 65
Dedicated CMOS I/O bit 66
Dedicated CMOS I/O bit 67
Dedicated CMOS I/O bit 68
Dedicated CMOS I/O bit 69
Dedicated CMOS I/O bit 70
Dedicated CMOS I/O bit 71
Dedicated CMOS I/O bit 72
Dedicated CMOS I/O bit 73
—
—
LVDS or CMOS clock out 2 or CMOS bit 76
Dedicated CMOS I/O bit 74
LVDS or CMOS clock out 2 or CMOS bit 77
Description
HSMB_D41
HSMB_D42
HSMB_D43
HSMB_D44
HSMB_D45
HSMB_D46
HSMB_D47
HSMB_D48
HSMB_D49
HSMB_D50
HSMB_D51
HSMB_D52
HSMB_D53
HSMB_D54
HSMB_D55
HSMB_D56
HSMB_D57
HSMB_D58
HSMB_D59
HSMB_D60
HSMB_D61
HSMB_D62
HSMB_D63
HSMB_D64
HSMB_D65
HSMB_D66
HSMB_D67
HSMB_D68
HSMB_D69
HSMB_D70
HSMB_D71
HSMB_D72
HSMB_D73
—
—
HSMB_CLKOUT_P2
HSMB_D74
HSMB_CLKOUT_N2
Schematic Signal
Arria II GX FPGA Development Board, 6G Edition Reference Manual
Name
LVDS or 2.5-V
I/O Standard
2.5-V
Pin Number
Arria II GX
Device
AC10
AC11
M10
AH3
AH6
AH4
AL2
AK3
AL1
AK1
AE5
AJ4
AJ3
AJ1
AJ2
M9
M8
M7
K8
K7
K6
G5
H7
G6
D5
G4
C6
D6
C5
N8
N7
L7
J8
J6
J7
F5
—
—
2–37