CD4046BCN Fairchild Semiconductor, CD4046BCN Datasheet

IC LOCK LOOP CMOS PHASE 16-DIP

CD4046BCN

Manufacturer Part Number
CD4046BCN
Description
IC LOCK LOOP CMOS PHASE 16-DIP
Manufacturer
Fairchild Semiconductor
Type
Phase Lock Loop (PLL)r
Datasheet

Specifications of CD4046BCN

Pll
No
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
No/No
Frequency - Max
1.6MHz
Divider/multiplier
No/No
Voltage - Supply
3 V ~ 15 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Through Hole
Package / Case
16-DIP (0.300", 7.62mm)
Frequency-max
1.3MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
4046
4046B
CD4046
© 2002 Fairchild Semiconductor Corporation
CD4046BCM
CD4046BCN
CD4046BC
Micropower Phase-Locked Loop
General Description
The CD4046BC micropower phase-locked loop (PLL) con-
sists of a low power, linear, voltage-controlled oscillator
(VCO), a source follower, a zener diode, and two phase
comparators. The two phase comparators have a common
signal input and a common comparator input. The signal
input can be directly coupled for a large voltage signal, or
capacitively coupled to the self-biasing amplifier at the sig-
nal input for a small voltage signal.
Phase comparator I, an exclusive OR gate, provides a digi-
tal error signal (phase comp. I Out) and maintains 90
phase shifts at the VCO center frequency. Between signal
input and comparator input (both at 50% duty cycle), it may
lock onto the signal input frequencies that are close to har-
monics of the VCO center frequency.
Phase comparator II is an edge-controlled digital memory
network. It provides a digital error signal (phase comp. II
Out) and lock-in signal (phase pulses) to indicate a locked
condition and maintains a 0 phase shift between signal
input and comparator input.
The linear voltage-controlled oscillator (VCO) produces an
output signal (VCO Out) whose frequency is determined by
the voltage at the VCO
tors connected to pin C1
The source follower output of the VCO
is used with an external resistor of 10 k
The INHIBIT input, when high, disables the VCO and
source follower to minimize standby power consumption.
The zener diode is provided for power supply regulation, if
necessary.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package Number
IN
A
input, and the capacitor and resis-
M16A
N16E
, C1
B
, R1 and R2.
IN
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
(demodulator Out)
or more.
DS005968
Features
Applications
• FM demodulator and modulator
• Frequency synthesis and multiplication
• Frequency discrimination
• Data synchronization and conditioning
• Voltage-to-frequency conversion
• Tone decoding
• FSK modulation
• Motor speed control
Wide supply voltage range:
Low dynamic power consumption: 70 W (typ.)
at f
VCO frequency: 1.3 MHz (typ.) at V
Low frequency drift: 0.06%/ C at V
temperature
High VCO linearity: 1% (typ.)
o
Package Description
10 kHz, V
DD
5V
October 1987
Revised March 2002
3.0V to 18V
DD
www.fairchildsemi.com
DD
10V with
10V

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CD4046BCN Summary of contents

Page 1

... Package Number CD4046BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4046BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Connection Diagram Block Diagram www.fairchildsemi.com Top View FIGURE 1. 2 ...

Page 3

Absolute Maximum Ratings (Note 2) DC Supply Voltage ( Input Voltage ( Storage Temperature Range ( Power Dissipation ( Dual-In-Line Small Outline Lead Temperature ( (Soldering, 10 ...

Page 4

AC Electrical Characteristics Symbol Parameter VCO SECTION I Operating Current DD f Maximum Operating Frequency MAX Linearity Temperature-Frequency Stability No Frequency Offset MIN Frequency Offset, f MIN VCO Input Resistance ...

Page 5

AC Electrical Characteristics Symbol Parameter VCO Offset Voltage IN V DEM Linearity ZENER DIODE V Zener Diode Voltage Z R Zener Dynamic Resistance Z Note 5: AC Parameters are guaranteed by DC correlated testing. Phase Comparator State Diagrams (Continued) Conditions ...

Page 6

Typical Waveforms FIGURE 3. Typical Waveform Employing Phase Comparator I in Locked Condition FIGURE 4. Typical Waveform Employing Phase Comparator II in Locked Condition www.fairchildsemi.com 6 ...

Page 7

Typical Performance Characteristics Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, P Comparator II, P (Total MIN Typical Center Frequency vs C1 for ...

Page 8

Typical Performance Characteristics Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, P Comparator II, P (Total MIN www.fairchildsemi.com (Continued) Typical R2/R1 MAX MIN FIGURE ...

Page 9

Typical Performance Characteristics Typical VCO Power Dissipation at f Typical Source Follower Power Dissipation vs R Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, P Comparator II, P (Total ...

Page 10

Typical Performance Characteristics FIGURE 11. Typical VCO Linearity vs R1 and C1 Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, P Comparator II, P (Total MIN www.fairchildsemi.com ...

Page 11

Design Information This information is a guide for approximating the value of external components for the CD4046B in a phase-locked- loop system. The selected external components must be within the following ranges: R1 ...

Page 12

Design Information (Continued) Using Phase Comparator I Characteristics VCO Without Offset R2 VCO Component Given Selection Use f with o Figure 5 to determine R1 and C1. References G.S. Moschytz, “Miniaturized RC Filters Using Phase-Locked Loop”, BSTJ, ...

Page 13

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 13 www.fairchildsemi.com ...

Page 14

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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