pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet
pi7c8150b
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pi7c8150b Summary of contents
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... PI7C8150B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE REVISION 2.02 3545 North First Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: 408-435-1100 Internet: http://www.pericom.com ...
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... No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies. 06-0044 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Page 2 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... Correction to description for bit[0] at offset 48h. Changed from Memory Read Flow Through Disable to Memory Read Flow Through Enable. Added reset condition to offset 4Ch, bits [31:28] Revised descriptions and added ordering information for PI7C8150B-33 (33MHz) device Revised temperature support to industrial temperature Revised temperature support back to extended commercial range (0C to 85C) Corrected pin descriptions for S_M66EN, P_M66EN, and S_CLKOUT ...
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... ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE This page intentionally left blank. Page 4 of 108 PI7C8150B APRIL 2006 – Revision 2.02 ...
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... FAST BACK-TO-BACK READ TRANSACTION ............................................................. 30 3.7 CONFIGURATION TRANSACTIONS ...................................................................................... 30 3.7.1 TYPE 0 ACCESS TO PI7C8150B....................................................................................... 31 3.7.2 TYPE 1 TO TYPE 0 CONVERSION .................................................................................. 31 3.7.3 TYPE 1 TO TYPE 1 FORWARDING................................................................................. 33 3.7.4 SPECIAL CYCLES ............................................................................................................. 33 3.8 TRANSACTION TERMINATION ............................................................................................. 34 3.8.1 MASTER TERMINATION INITIATED BY PI7C8150B ................................................. 35 3.8.2 MASTER ABORT RECEIVED BY PI7C8150B ................................................................ 36 3.8.3 TARGET TERMINATION RECEIVED BY PI7C8150B.................................................. 36 3.8.4 TARGET TERMINATION INITIATED BY PI7C8150B.................................................. 38 4 ADDRESS DECODING..................................................................................................................... 40 4.1 ADDRESS RANGES ................................................................................................................... 40 4.2 I/O ADDRESS DECODING........................................................................................................ 40 4.2.1 I/O BASE AND LIMIT ADDRESS REGISTER ...
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... POSTED WRITE TRANSACTIONS.................................................................................. 54 6.3 DATA PARITY ERROR REPORTING SUMMARY................................................................. 55 6.4 SYSTEM ERROR (SERR_L) REPORTING............................................................................... 59 7 EXCLUSIVE ACCESS ...................................................................................................................... 60 7.1 CONCURRENT LOCKS ............................................................................................................. 60 7.2 ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B .................................................... 60 7.2.1 LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION ..................................... 60 7.2.2 LOCKED TRANSACTION IN UPSTREAM DIRECTION .............................................. 62 7.3 ENDING EXCLUSIVE ACCESS................................................................................................ 62 8 PCI BUS ARBITRATION................................................................................................................. 63 8.1 PRIMARY PCI BUS ARBITRATION ........................................................................................ 63 8 ...
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... GPIO DATA AND CONTROL REGISTER – OFFSET 64h ........................................ 88 14.1.40 SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ................................. 88 14.1.41 P_SERR_L STATUS REGISTER – OFFSET 68h ........................................................ 89 14.1.42 PORT OPTION REGISTER – OFFSET 74h ................................................................ 90 14.1.43 RETRY COUNTER REGISTER – OFFSET 78h .......................................................... 91 06-0044 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Page 7 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... TIMING........................................................................................................................ 104 17.5 33MHZ TIMING........................................................................................................................ 105 17.6 POWER CONSUMPTION ........................................................................................................ 105 18 PACKAGE INFORMATION...................................................................................................... 106 18.1 208-PIN FQFP PACKAGE DIAGRAM .................................................................................... 106 18.2 256-BALL PBGA PACKAGE DIAGRAM ............................................................................... 107 18.3 PART NUMBER ORDERING INFORMATION...................................................................... 107 06-0044 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Page 8 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... RRORS F .................................................................................................. 68 ORMAT T ...................................................................................... 70 RANSITIONS R O .................................................................................... 100 EGISTER RDER E ............................................................................................ 64 XAMPLE B D ................................................................................. 97 LOCK IAGRAM M C ............................................................ 104 EASUREMENT ONDITIONS O ..................................................................................... 106 UTLINE O .................................................................................... 107 ACKAGE UTLINE Page 9 of 108 PI7C8150B .................................................... 26 B .......................................... ............................................ ......................... 56 ETECTED .................... 57 RROR ETECTED IT APRIL 2006 – Revision 2.02 ...
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... ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE This page intentionally left blank. Page 10 of 108 PI7C8150B APRIL 2006 – Revision 2.02 ...
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... Revision 2.3. Both the primary and secondary interfaces are specified to run at 32-bits and up to 66MHz (33MHz for PI7C8150B-33). Product Features • 32-bit Primary and Secondary Ports run up to 66MHz (33MHz for PI7C8150B-33) • Compliant with the PCI Local Bus Specification, Revision 2.3 • ...
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... P_TRDY_L is asserted. Data is transferred on rising clock edges when both P_IRDY_L and P_TRDY_L are asserted. During bus idle, PI7C8150B drives P_AD to a valid logic level when P_GNT_L is asserted. Primary Command/Byte Enables: Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins ...
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... Primary Request (Active LOW): This is asserted by PI7C8150B to indicate that it wants to start a transaction on the primary bus. PI7C8150B de-asserts this pin for at least 2 PCI clock cycles before asserting it again. Primary Grant (Active LOW): When asserted, PI7C8150B can access the primary bus. During idle and P_GNT_L asserted, PI7C8150B will drive P_AD, P_CBE, and P_PAR to valid logic levels ...
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... Page 14 of 108 PI7C8150B Description Primary Interface 66MHz Operation. This input is used to specify if PI7C8150B is capable of running at 66MHz. For 66MHz operation on the Primary bus, this signal should be pulled “HIGH”. For 33MHz operation on the Primary bus, this signal should be pulled LOW. In synchronous mode, S_M66EN will be driven LOW, forcing the secondary bus to run at 33MHz also ...
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... The input is externally pulled up through a resistor to VDD. Secondary Grant (Active LOW): PI7C8150B asserts this pin to access the secondary bus. PI7C8150B de- asserts this pin for at least 2 PCI clock cycles before asserting it again. During idle and S_GNT_L asserted, PI7C8150B will drive S_AD, S_CBE, and S_PAR. ...
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... S_VIO must be tied to 3.3V only when all devices on the secondary bus use 3.3V signaling. Otherwise, S_VIO is tied to 5V. Bus/Power Clock Control Management Pin: When this pin is tied HIGH and the PI7C8150B is placed in the D3 power state, it enables the PI7C8150B to place HOT the secondary bus in the B2 power state. The secondary clocks are disabled and driven to 0 ...
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... Description Test Clock. Used to clock state information and data into and out of the PI7C8150B during boundary scan. Test Mode Select. Used to control the state of the Test Access Port controller. Test Data Output. When SCAN_EN_H is HIGH used (in conjunction with TCK) to shift data out of the Test Access Port (TAP serial bit stream ...
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... Page 18 of 108 PI7C8150B Description Power: +3.3V Digital power. Ground: Digital ground. Name Type S_REQ_L[1] I S_REQ_L[3] I S_REQ_L[5] I S_REQ_L[7] I S_GNT_L[0] TS VSS P S_GNT_L[3] TS S_GNT_L[5] TS S_GNT_L[7] TS VSS P S_RESET_L O GPIO[3] TS VDD ...
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... S_AD[5] P 146 S_AD[6] TS 148 VSS TS 150 S_AD[8] P 152 S_AD[9] I/OD 154 S_AD[10] I 156 VSS P 158 VSS TS 160 VSS Page 19 of 108 APRIL 2006 – Revision 2.02 PI7C8150B Type STS STS STS P ...
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... S_REQ_L[ VDD P P E10 VDD P P E13 S_AD[ E16 S_AD[ S_GNT_L[ VSS VSS P Page 20 of 108 PI7C8150B Name Type S_AD[13] TS S_AD[14] TS VSS P S_PAR TS VDD P S_LOCK_L STS VSS P S_TRDY_L STS VDD P S_CBE[2] TS S_AD[16] TS VDD P S_AD[19] TS S_AD[20] TS VDD ...
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... R13 P_AD[12 R16 MS1 VDD P_AD[23 P_AD[16] TS STS T12 P_PERR_L STS TS T15 P_AD[10] TS Page 21 of 108 PI7C8150B Pin Name Type Number F13 S_AD[5] TS F16 S_AD[ S_GNT_L[ VSS P G9 VSS P G12 VDD P G15 TRST_L I H2 S_CFN_L ...
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... Table 3-1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C8150B initiates transactions as a master, on the primary (P) and secondary (S) buses, and when PI7C8150B responds to transactions as a target, on the primary (P) and secondary (S) buses. ...
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... P_CBE[3:0]. PI7C8150B supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. If either of the lowest two address bits is nonzero, PI7C8150B automatically disconnects the transaction after the first data transfer. ...
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... Once the posted write data moves to the head of the posted data queue, PI7C8150B asserts its request on the target bus. This can occur while PI7C8150B is still receiving data on the initiator bus. When the grant for the target bus is received and the target bus is detected in the idle condition, PI7C8150B asserts FRAME_L and drives the stored write address out on the target bus ...
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... The PI7C8150B initiates the transaction on the target bus. PI7C8150B transfers the write data to the target. If PI7C8150B receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered ...
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... If the initiator repeats the write transaction before the data has been transferred to the target, PI7C8150B returns a target retry to the initiator. PI7C8150B continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, PI7C8150B does not make a new entry into the delayed transaction queue ...
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... However, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-prefetchable read transaction. For prefetchable read transactions, PI7C8150B forces all byte enable bits to be turned on for all data phases. Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space ...
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... READ PREFETCH ADDRESS BOUNDARIES PI7C8150B imposes internal read address boundaries on read pre-fetched data. When a read transaction reaches one of these aligned address boundaries, the PI7C8150B stops pre- fetched data, unless the target signals a target disconnect before the read pre-fetched boundary is reached. When PI7C8150B finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered ...
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... If the read transaction is a non-prefetchable read, PI7C8150B drives the captured byte enable bits during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all data phases. If PI7C8150B receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered ...
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... PI7C8150B also conditionally asserts P_SERR_L (see Section 6.4). PI7C8150B has the capability to post multiple delayed read requests maximum of four in each direction initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted already contained in the delayed transaction queue ...
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... PI7C8150B generates a Type 0 transaction only on the secondary bus, and never on the primary bus. PI7C8150B responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase: ...
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... Fh 10h – 1Eh 1Fh PI7C8150B can assert unique address lines to be used as IDSEL signals for devices on the secondary bus, for device numbers ranging from 0 through 8. Because of electrical loading constraints of the PCI bus, more than 9 IDSEL signals should not be necessary. However, if device numbers greater than 9 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted ...
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... PI7C8150B forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer. 3.7.3 TYPE 1 TO TYPE 1 FORWARDING Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-to-PCI bridges are used. ...
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... PI7C8150B initiates a special cycle on the target bus when a Type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase: The lowest two address bits on AD[1:0] are equal to 01b. The device number in address bits AD[15:11] is equal to 11111b. ...
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... MASTER TERMINATION INITIATED BY PI7C8150B PI7C8150B initiator, uses normal termination if DEVSEL_L is returned by target within five clock cycles of PI7C8150B’s assertion of FRAME_L on the target bus initiator, PI7C8150B terminates a transaction when the following conditions are met: During a delayed write transaction, a single DWORD is delivered. ...
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... The transaction is then removed from the delayed transaction queue. When a master abort is received in response to a posted write transaction, PI7C8150B discards the posted write data and makes no more attempts to deliver the data. PI7C8150B sets the received-master-abort bit in the status register when the master abort is received on the primary bus sets the received master abort bit in the secondary status register when the master abort is received on the secondary interface ...
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... Target Abort After the PI7C8150B makes 2 on the target bus, PI7C8150B asserts P_SERR_L if the SERR_L enable bit (bit 8 of command register for the secondary bus) is set and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h) ...
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... Target Disconnect Target Abort After PI7C8150B makes 2 target bus, PI7C8150B asserts P_SERR_L if the primary SERR_L enable bit is set (bit 8 of command register for secondary bus) and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h). ...
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... Otherwise, the transaction is discarded from the buffers. 3.8.4.2 TARGET DISCONNECT PI7C8150B returns a target disconnect to an initiator when one of the following conditions is met: PI7C8150B hits an internal address boundary. 06-0044 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Page 39 of 108 APRIL 2006 – ...
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... See Section 3.5.4 for a description of write address boundaries, and Section 3.6.3 for a description of read address boundaries. 3.8.4.3 TARGET ABORT PI7C8150B returns a target abort to an initiator when one of the following conditions is met: PI7C8150B is returning a target abort from the intended target. When PI7C8150B returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface ...
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... I/O enable bit is not set. To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the master- enable bit is not set, PI7C8150B ignores all I/O and memory transactions initiated on the secondary bus. The master-enable bit also allows upstream forwarding of memory transactions set. ...
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... All other I/O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O address range. When the ISA enable bit is set, devices downstream of PI7C8150B can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary ...
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... Read transactions to non-prefetchable space may exhibit side effects; this space may have non-memory-like behavior. PI7C8150B prefetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer ...
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... PI7C8150B ignores memory transactions initiated on the secondary interface that fall into this address range. PI7C8150B does not respond to any transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into the memory-mapped I/O range or are not forwarded by the VGA mechanism) ...
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... PI7C8150B provides VGA snoop mode, allowing for VGA palette write transactions to be forwarded downstream. This mode is used when a graphics device downstream from PI7C8150B needs to snoop or respond to VGA palette write transactions. To enable the mode, set the VGA snoop bit in the command register in configuration space. Note that PI7C8150B claims VGA palette write transactions by asserting DEVSEL_L in VGA snoop mode ...
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... Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C8150B behaves in the same way as if only the VGA mode bit were set. 5 TRANSACTION ORDERING To maintain data coherency and consistency, PI7C8150B complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.3, for transactions crossing the bridge ...
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... The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C8150B and must also be true for other bus agents. Otherwise, a deadlock can occur. PI7C8150B accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across PI7C8150B ...
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... A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data traveling in the same direction. In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C8150B as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator ...
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... PI7C8150B checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, PI7C8150B always tries to forward the existing parity condition on one bus to the other bus, along with address and data. PI7C8150B always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions ...
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... When PI7C8150B detects an address parity error on the secondary interface, the following events occur: If the parity error response bit is set in the bridge control register, PI7C8150B does not claim the transaction with S_DEVSEL_L; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally and accepts transaction directed to or across PI7C8150B ...
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... PI7C8150B sets the detected parity error bit in the status register, regardless of the state of the parity error response bit. 6.2.2 READ TRANSACTIONS When PI7C8150B detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts PERR_L. For ...
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... PI7C8150B sets the secondary interface data parity detected bit in the secondary status register, if the secondary parity error response bit is set in the bridge control register. PI7C8150B captures the parity error condition to forward it back to the initiator on the primary bus. Similarly, for upstream transactions, when PI7C8150B is delivering data to the target on ...
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... PI7C8150B captures the parity error condition to forward it back to the initiator on the secondary bus. A delayed write transaction is completed on the initiator bus when the initiator repeats the write transaction with the same address, command, data, and byte enable bits as the delayed write command that is at the head of the posted data queue. Note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues ...
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... PI7C8150B asserts P_PERR_L two cycles after the data transfer, if the parity error response bit is set in the command register of primary interface. PI7C8150B sets the parity error detected bit in the status register of the primary interface. PI7C8150B captures and forwards the bad parity condition to the secondary bus. ...
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... During upstream write transactions, when a data parity error is reported on the target (primary) bus by the target’s assertion of P_PERR_L, the following events occur: PI7C8150B sets the data parity detected bit in the status register, if the parity error response bit is set in the command register of the primary interface. ...
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... X = don’t care Table 6-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C8150B detects a parity error on the secondary interface. Table 6-2. Setting Secondary Interface Detected Parity Error Bit Secondary Detected ...
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... X= don’t care Table 6-5 shows assertion of P_PERR_L. This signal is set under the following conditions: PI7C8150B is either the target of a write transaction or the initiator of a read transaction on the primary bus. The parity-error-response bit must be set in the command register of primary interface. PI7C8150B detects a data parity error on the primary bus or detects S_PERR_L asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus ...
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... The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. Table 6-6 shows assertion of S_PERR_L that is set under the following conditions: PI7C8150B is either the target of a write transaction or the initiator of a read transaction on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface ...
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... PI7C8150B did not detect the parity error as a target of the posted write transaction. The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. The SERR_L enable bit must be set in the command register. ...
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... CONCURRENT LOCKS The primary and secondary bus lock mechanisms operate concurrently except when a locked transaction crosses PI7C8150B. A primary master can lock a primary target without affecting the status of the lock on the secondary bus, and vice versa. This means that a primary master can lock a primary target at the same time that a secondary master locks a secondary target ...
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... Note that the existing lock on the target bus could not have crossed PI7C8150B. Otherwise, the pending queued locked transaction would not have been queued. When PI7C8150B is able to complete a data transfer with the locked read transaction, the lock is established on the secondary bus. ...
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... LOCK_L on the target bus at the end of the transaction because the lock was relinquished at the end of the write transaction on the initiator bus. When PI7C8150B receives a target abort or a master abort in response to a locked delayed transaction, PI7C8150B returns a target abort or a master abort when the initiator repeats the locked transaction ...
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... PCI clock cycle. When P_GNT_L is asserted to PI7C8150B when P_REQ_L is not asserted, PI7C8150B parks P_AD, P_CBE, and P_PAR by driving them to valid logic levels. When the primary bus is parked at PI7C8150B and PI7C8150B has a transaction to initiate on the primary bus, PI7C8150B starts the transaction if P_GNT_L was asserted during the previous cycle ...
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... B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6, B, m0, m1, m2, m7 and so on. Each bus master, including PI7C8150B, can be configured either the low priority group or the high priority group by setting the corresponding priority bit in the arbiter- control register. The arbiter-control register is located at offset 40h. Each master has a corresponding bit ...
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... PI7C8150B parks the secondary bus at itself until transactions start occurring on the secondary bus. Offset 48h, bit 1, can be set park the secondary bus at PI7C8150B. By default, offset 48h, bit 1, is set the internal arbiter is disabled, PI7C8150B parks 06-0044 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Page 65 of 108 APRIL 2006 – ...
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... PI7C8150B-33 can be run in the following frequency configuration: To set asynchronous mode support, MS0 and MS1 must be configured accordingly: When MS0 and MS1 are pulled to HIGH during the deassertion of P_RST, PI7C8150B will go into asynchronous mode. The secondary clock outputs will then be derived from ...
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... During secondary interface reset, the GPIO interface can be used to shift in a 16-bit serial stream that serves as a secondary bus clock disable mask. Along with the GPIO[3] pin, a live insertion bit can be used to bring the PI7C8150B to a halt through hardware, permitting live insertion of option cards behind the PI7C8150B ...
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... The rest value for the output is 0. 10.2 SECONDARY CLOCK CONTROL The PI7C8150B uses the GPIO pins and the MSK_IN signal to input a 16-bit serial data stream. This data stream is shifted into the secondary clock control register and is used for selectively disabling secondary clock outputs. ...
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... When live insertion mode is enabled, whenever GPIO[3] is driven to a value of 1, the I/O enable, the memory enable, and the master enable bits are internally masked to 0. This means that target, PI7C8150B no longer accepts any I/O or memory transactions, on either interface. When read, the register bits still reflect the value originally written by a configuration write command ...
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... Support for D0, D3 Support for D0, D1, D2, D3 behind the bridge Support of the B2 secondary bus power state when in the D3 state Table 11-1 shows the states and related actions that PI7C8150B performs during power management transitions. (No other transactions are permitted.) Table 11-1. Power Management Transitions Current Status D0 ...
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... CHIP RESET The chip reset bit in the diagnostic control register can be used to reset the PI7C8150B and the secondary bus. When the chip reset bit is set, all registers and chip state are reset and all signals are tristated ...
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... Type 1 Configuration Write. 3. Otherwise, ignore. Configuration Write as Special Cycle Request (device = 1Fh, function = 7h the target bus is the bridges secondary bus: claim and pass through as a special cycle. Page 72 of 108 PI7C8150B APRIL 2006 – Revision 2.02 ...
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... Memory Read Same as Memory Read Multiple Dual Address Cycle Supported Memory Read Line Same as Memory Read Memory Write and Same as Memory Read Invalidate Page 73 of 108 PI7C8150B APRIL 2006 – Revision 2.02 ...
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... CONFIGURATION REGISTERS PCI configuration defines a 64-byte space (configuration header) to define various attributes of PI7C8150B as shown below. 14.1 CONFIGURATION REGISTER 31-24 Reserved Secondary Latency Timer Secondary Status Prefetchable Memory Limit I/O Limit Upper 16-bit Upstream Memory Control Secondary Bus Arbiter Preemption Control Upstream ( Memory Limit ...
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... ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Type Description R/O Identifies Pericom as vendor of this device. Hardwired as 12D8h. Type Description R/O Identifies this device as the PI7C8150B. Hardwired as 8150h. Type Description Controls response to I/O access on the primary interface 0: ignore I/O transactions on the primary interface R/W 1: enable response to I/O transactions on the primary interface Reset to 0 ...
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... Set to 1 (by a target device) whenever a target abort cycle occurs Reset to 0 R/WC Set to 1 (by a master device) whenever transactions are terminated with target aborts Reset to 0 R/WC Set to 1 (by a master) when transactions are terminated with Master Abort Reset to 0 Page 76 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... This register sets the value for the Master Latency Timer, which starts counting when the master asserts FRAME_L. Reset to 0 Type Description R/O Read as 01h to indicate that the register layout conforms to the standard PCI-to-PCI bridge layout. Page 77 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... The upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed The upper 16 bits corresponding to address bits [31:16] are defined in the I/O base address upper 16 bits address register Reset to 0 Page 78 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... Set to 1 (by a master) when transactions on its secondary interface are terminated with Master Abort R/WC Reset to 0 Set to 1 when S_SERR_L is asserted R/WC Reset to 0 Set to 1 when address or data parity error is detected on the secondary interface R/WC Reset to 0 Page 79 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... Defines the top address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed to be FFFFFh. Page 80 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... Type Description R/O Enhanced capabilities port offset pointer. Read as DCh to indicate that the first item resides at that configuration offset. Type Description R/W For POST to program to FFh, indicating that the PI7C8150B does not implement an interrupt pin. Page 81 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... Master Abort Mode 06-0044 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Type Description R/O Interrupt pin not supported on the PI7C8150B Type Description R/W Controls the bridge’s response to parity errors on the secondary interface. 0: ignore address and data parity errors on the secondary interface 1: enable parity error reporting and detection on the secondary ...
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... Controls when the bridge (as a target) disconnects memory write transactions. 0: memory write disconnects at 4KB aligned address boundary 1: memory write disconnects at cache line aligned address boundary Reset to 0 R/O Reserved. Returns 0 when read. Reset to 0. Page 83 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... Enables hardware control of transaction forwarding. 0: GPIO[3] has no effect on the I/O, memory, and master enable bits 1: If GPIO[3] is set to input mode, this bit enables GPIO[3] to mask I/O enable, memory enable and master enable bits to 0. PI7C8150B will stop accepting I/O and memory transactions as a result. Reset to 0 R/O Reserved ...
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... Upstream memory is the entire range except the down stream memory channel R/W 1: Upstream memory is confined to upstream Memory Base and th th Limit (See offset 50 and 54 for upstream memory range) Reset to 0 R/O Reserved. Returns 0 when read. Reset to 0 Page 85 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... Description 0: 32 bit addressing R bit addressing Reset to 1 Controls upstream memory base address. R/W Reset to 00000000h Type Description 0: 32 bit addressing R bit addressing Reset to 1 Controls upstream memory limit address. R/W Reset to 000FFFFFh Page 86 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... R/W bit in the command register is set 1: P_SERR_L is not asserted if this event occurs Reset to 0 Controls PI7C8150B’s ability to assert P_SERR_L when it receives a master abort when attempting to deliver posted write data. 0: P_SERR# is asserted if this event occurs and the SERR# enable bit R/W in the command register is set ...
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... Function 1:0 Clock 0 disable 06-0044 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Type Description Controls PI7C8150B’s ability to assert P_SERR# when it is unable to 24 transfer delayed write data after 2 attempts. 0: P_SERR_L is asserted if this event occurs and the SERR_L enable R/W bit in the command register is set ...
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... Signal P_SERR_L was asserted because the bridge was unable to 24 read any data from the target after 2 R/WC Reset Signal P_SERR_L was asserted because a master did not repeat a read or write transaction before master timeout. R/WC Reset to 0. Page 89 of 108 APRIL 2006 – Revision 2.02 PI7C8150B 24 attempts. attempts. ...
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... Controls PI7C8150B’s detection mechanism for matching non-posted memory write and invalidate cycles from the initiator on the secondary interface R/W 0: When accepting MEMWI command at the secondary interface, PI7C8150B converts MEMWI to MEMW command on the primary interface 1: Disconnects MEMWI command at aligned cache line boundaries Page 90 of 108 APRIL 2006 – Revision 2.02 ...
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... FIFO or until terminated by target Reset to 1 R/O Reserved. Returns 0 when read. Reset to 0. Type Description Holds the maximum number of attempts that PI7C8150B will try R/W before reporting retry timeout. Retry count set at 2 Default is 0100 0000h. Type Description There are 2 control settings for the secondary bus master timeout counter ...
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... Reset to 04h Type Description Reset to 0000 0000: next pointer (00h if MS0=0 and MS1=1, or R/O MS0=1) Type Description Determines expansion slot number R/W Reset to 0 First in chassis R/W Reset to 0 R/O Reserved. Returns 0 when read. Reset to 0. Page 92 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... Read as 001 to indicate the device is compliant to Revision 1.0 of R/O PCI Power Management Interface Specifications. R/O Read indicate PI7C8150B does not support the PME# pin. Read indicate PI7C8150B does not support the PME# pin or R/O an auxiliary power source. Read indicate PI7C8150B does not have device specific R/O initialization requirements ...
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... D3 state Reset to 0 R/O Read as 0 R/O Read PI7C8150B does not support the PME# pin. R/O Read the data register is not implemented. R/O Read the data register is not implemented. R/O Read the PME# pin is not implemented. Type Description 00h: Reserved ...
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... ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) 15.2.1 MASTER ABORT Master abort indicates that when PI7C8150B acts as a master and receives no response (i.e., no target asserts DEVSEL_L or S_DEVSEL_L) from a target, the bridge de-asserts FRAME_L and then de-asserts IRDY_L. 15.2.2 PARITY AND ERROR REPORTING Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, and S_PAR signals. Parity should be even ( even number of‘ ...
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... Master Abort. 15.2.4 SECONDARY IDSEL MAPPING When PI7C8150B detects a Type 1 configuration transaction for a device connected to the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11 device number. This is translated to S_AD[31:16] by PI7C8150B. ...
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... TAP PINS The PI7C8150B’s TAP pins form a serial port composed of four input connections (TMS, TCK, TRST_L and TDI) and one output connection (TDO). These pins are described in Table 16-1. The TAP pins provide access to the instruction register and the test data registers ...
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... TDI shifts, and becomes active on the falling edge of TCK. 16.2 BOUNDARY SCAN INSTRUCTION SET The PI7C8150B supports three mandatory boundary-scan instructions (BYPASS, SAMPLE and EXTEST). The table shown below lists the PI7C8150B’s boundary-scan instruction codes. Table 16-1. TAP Pins Instruction / ...
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... The boundary-scan register contains a cell for each pin as well as control cells for I/O and the high-impedance pin. Table 16-1 shows the bit order of the PI7C8150B boundary-scan register. All table cells that contain “Control” select the direction of bi-directional pins or high-impedance output pins. When a “1” is loaded into the control cell, the associated pin(s) are high-impedance or selected as output ...
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... S_AD[26] 198 S_AD[27] 200 S_AD[28] 201 S_AD[29] 203 S_AD[30] 204 S_AD[31] 206 S_REQ_L[0] 207 S_REQ_L[1] 2 Page 100 of 108 APRIL 2006 – Revision 2.02 PI7C8150B Type BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR OUTPUT BIDIR BIDIR BIDIR BIDIR BIDIR ...
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... P_AD[22] 68 P_AD[21] 70 P_AD[20] 71 P_AD[19] 73 P_AD[18] 74 P_AD[17] 76 P_AD[16] 77 P_CBE[2] 79 P_FRAME_L 80 P_IRDY_L 82 Page 101 of 108 APRIL 2006 – Revision 2.02 PI7C8150B Type INPUT INPUT INPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT CONTROL OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT OUTPUT INPUT BIDIR BIDIR ...
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... ELECTRICAL AND TIMING SPECIFICATIONS 17.1 MAXIMUM RATINGS (Above which the useful life may be impaired. For user guidelines, not tested). Storage Temperature Ambient Temperature with Power Applied – PI7C8150B Ambient Temperature with Power Applied – PI7C8150BI Supply Voltage to Ground Potentials (AV Voltage at Input Pins Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device ...
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... 0. -500μA DD out I = 1500μA out V – 0 -500μA DD out I = 1500μA out 5 of the input device. DD Page 103 of 108 APRIL 2006 – Revision 2.02 PI7C8150B Max. Units Notes ± ...
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... P_CLK, S_CLKOUT[9:0] HIGH time HIGH T P_CLK, S_CLKOUT[9:0] LOW time LOW 06-0044 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE PCI Signal Timing Measurement Conditions Min. 1,2,3 3 1,2,3 5 1,2 0 1,2,3 2 1,2,3 2 1,2 2 1,2 - Condition 20pF load Page 104 of 108 PI7C8150B 66 MHz 33 MHz Max. Min. Max. Units - 10 ...
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... P_CLK, S_CLKOUT[9:0] LOW time LOW 17.6 POWER CONSUMPTION Parameter Power Consumption at 66MHz Supply Current 06-0044 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Condition 20pF load Typical 1.68 510 Page 105 of 108 APRIL 2006 – Revision 2.02 PI7C8150B Min. Max. Units 0 0.250 3.14 5. Units W mA ...
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... PACKAGE INFORMATION 18.1 208-PIN FQFP PACKAGE DIAGRAM Figure 18-1 06-0044 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE 208-pin FQFP Package Outline Page 106 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...
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... PART NUMBER ORDERING INFORMATION Part Number PI7C8150BMA PI7C8150BND PI7C8150BMA-33 PI7C8150BND-33 PI7C8150BMAE PI7C8150BNDE PI7C8150BMAI PI7C8150BNDI PI7C8150BMAI-33 PI7C8150BNDI-33 PI7C8150BMAIE PI7C8150BNDIE 06-0044 ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE 256-pin PBGA Package Outline http://www.pericom.com/packaging/mechanicals.php Speed Pin – Package 66 MHz 208 – FQFP 66 MHz 256 – PBGA 33 MHz 208 – ...
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... ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE NOTES: Page 108 of 108 APRIL 2006 – Revision 2.02 PI7C8150B ...