PIC12F635-I/P Microchip Technology, PIC12F635-I/P Datasheet - Page 122
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PIC12F635-I/P
Manufacturer Part Number
PIC12F635-I/P
Description
IC MCU FLASH 1KX14 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F635-ISN.pdf
(234 pages)
2.PIC12F635-ISN.pdf
(8 pages)
3.PIC16F636-IST.pdf
(196 pages)
Specifications of PIC12F635-I/P
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
8-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
5
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS- 232/SPI/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029, DV164101, DM163014
Minimum Operating Temperature
- 40 C
Data Rom Size
128 B
Height
3.3 mm
Length
9.27 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM163029 - BOARD PICDEM FOR MECHATRONICSAC162057 - MPLAB ICD 2 HEADER 14DIPACICE0201 - MPLABICE 8P 300 MIL ADAPTERAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12F635-I/P
Manufacturer:
VICOR
Quantity:
32
- Current page: 122 of 234
- Download datasheet (4Mb)
PIC12F635/PIC16F636/639
FIGURE 11-18:
DS41232D-page 120
LFDATA/RSSI/
MCU SPI Read Details:
1.
2.
3.
4.
5.
6.
SCLK/ALERT
Note:
CCLK/SDIO
Drive the AFE’s open collector ALERT output low.
•
Drop CS
•
•
Change LFDATA/RSSI/CCLK/SDIO connected pin to output.
•
Clock in 16-bit SPI Read sequence.
•
Change LFDATA/RSSI/CCLK/SDIO connected pin to input.
Raise CS to complete the SPI Read entry of command and address.
CS
To ensure no false clocks occur when CS drops.
AFE SCLK/ALERT becomes SCLK input.
LFDATA/RSSI/CCLK/SDIO becomes SDI input.
Driving SPI data.
Command, address and dummy data.
(output)
ALERT
The T
Configuration register data appears at 6th clock after T
LFDATA
(output)
1
CSH
(input)
(input)
SCLK
SDI
T
2
CSSC
is considered as one clock. Therefore, the
SPI READ SEQUENCE
T
SU
MSb
T
3
HD
4
16 Clocks for Read Command,
Address and Dummy Data
T
1/F
HI
SCLK
T
LO
CSH
LSb
.
T
SCCS
6
5
7.
8.
9.
10.
T
LFDATA
(output)
CS
(output)
ALERT
1
T
Drop CS.
•
•
Clock out 16-bit SPI Read result.
•
•
•
Raise CS to complete the SPI Read.
Change SCLK/ALERT back to input.
CSH
T
CS
AFE SCLK/ALERT becomes SCLK input.
LFDATA/RSSI/CCLK/SDIO becomes SDO output.
First seven bits clocked-out are dummy bits.
Next eight bits are the Configuration register data.
The last bit is the Configuration register row parity bit.
0
(input)
(output)
SCLK
T
SDO
7
CSSC
8
16 Clocks for Read Result
© 2007 Microchip Technology Inc.
T
DO
T
CSSC
9
T
LFDATA
(output)
CS
(output)
1
ALERT
10
T
CSH
T
CS
0
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