PIC12F635-I/P Microchip Technology, PIC12F635-I/P Datasheet - Page 90

• Manufacturer Part Number: PIC12F635-I/P
• Description: IC MCU FLASH 1KX14 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F635-I/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 5
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232/SPI/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029, DV164101, DM163014
• Minimum Operating Temperature: - 40 C
• Data Rom Size: 128 B
• Height: 3.3 mm
• Length: 9.27 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163029 - BOARD PICDEM FOR MECHATRONICSAC162057 - MPLAB ICD 2 HEADER 14DIPACICE0201 - MPLABICE 8P 300 MIL ADAPTERAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F635/PIC16F636/639
8.1
To setup the PLVD for operation, the following steps
must be taken:
• Enable the module by setting the LVDEN bit of the
• Configure the trip point by setting the LVDL<2:0>
• Wait for the reference voltage to become stable.
• Clear the LVDIF bit of the PIRx register.
The LVDIF bit will be set when V
PLVD trip point. The LVDIF bit remains set until cleared
by software. Refer to Figure 8-2.
8.2
The PLVD trip point is selectable from one of eight
voltage levels. The LVDL bits of the LVDCON register
select the trip point. Refer to Register 8-1 for the
available PLVD trip points.
8.3
When V
edge detector will set the LVDIF bit. See Figure 8-2. An
interrupt will be generated if the following bits are also
set:
• GIE and PEIE bits of the INTCON register
• LVDIE bit of the PIEx register
The LVDIF bit must be cleared by software. An interrupt
can be generated from a simulated PLVD event when
the LVDIF bit is set by software.
DS41232D-page 88
LVDCON register.
bits of the LVDCON register.
Refer to Section 8.4 “Stable Reference
Indication”.
DD
PLVD Operation
Programmable Trip Point
Interrupt on Falling V
falls below the PLVD trip point, the falling
DD
DD
falls below the
8.4
When the PLVD module is enabled, the reference volt-
age must be allowed to stabilize before the PLVD will
provide a valid result. Refer to Electrical Section,
PLVD Characteristics for the stabilization time.
When the HFINTOSC is running, the IRVST bit of the
LVDCON register indicates the stability of the voltage
reference. The voltage reference is stable when the
IRVST bit is set.
8.5
To wake from Sleep, set the LVDIE bit of the PIEx
register and the PEIE bit of the INTCON register. When
the LVDIE and PEIE bits are set, the device will wake
from Sleep and execute the next instruction. If the GIE
bit is also set, the program will call the Interrupt Service
Routine upon completion of the first instruction after
waking from Sleep.
Stable Reference Indication
Operation During Sleep
© 2007 Microchip Technology Inc.