PIC18F1230-I/SO Microchip Technology, PIC18F1230-I/SO Datasheet
PIC18F1230-I/SO
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PIC18F1230-I/SO Summary of contents
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... High-Performance Microcontrollers with 10-bit A/D and nanoWatt Technology 2009 Microchip Technology Inc. PIC18F1230/1330 Data Sheet DS39758D ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F1230 4096 2048 PIC18F1330 8192 4096 2009 Microchip Technology Inc. PIC18F1230/1330 Peripheral Highlights: • High-Current Sink/Source 25 mA/25 mA • Programmable External Interrupts • Four Input Change Interrupts • Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN/J2602 - RS-232 operation using internal oscillator ...
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... PIC18F1230/1330 Pin Diagrams 18-Pin PDIP, SOIC RA0/AN0/INT0/KBI0/CMP0 RA1/AN1/INT1/KBI1 RA4/T0CKI/AN2/V + REF MCLR/V /RA5/FLTA ( / RA2/TX/CK RA3/RX/DT RB0/PWM0 RB1/PWM1 20-Pin SSOP RA0/AN0/INT0/KBI0/CMP0 RA1/AN1/INT1/KBI1 RA4/T0CKI/AN2/V + REF (2) MCLR/V /RA5/FLTA RA2/TX/CK RA3/RX/DT RB0/PWM0 RB1/PWM1 Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of Note 1: CONFIG3H. Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. ...
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... Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of Note 1: CONFIG3H. Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H recommended that the user connect the center metal pad for this device package to the ground. 3: 2009 Microchip Technology Inc. PIC18F1230/1330 ...
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... PIC18F1230/1330 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with PIC18F Microcontrollers ..................................................................................................... 17 3.0 Oscillator Configurations ............................................................................................................................................................ 21 4.0 Power-Managed Modes ............................................................................................................................................................. 31 5.0 Reset .......................................................................................................................................................................................... 39 6.0 Memory Organization ................................................................................................................................................................. 51 7.0 Flash Program Memory .............................................................................................................................................................. 71 8.0 Data EEPROM Memory ............................................................................................................................................................. 81 9 Hardware Multiplier............................................................................................................................................................ 85 10.0 I/O Ports ..................................................................................................................................................................................... 87 11.0 Interrupts .................................................................................................................................................................................... 93 12 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2009 Microchip Technology Inc. PIC18F1230/1330 DS39758D-page 7 ...
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... PIC18F1230/1330 NOTES: DS39758D-page 8 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F1230/1330 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F1230/1330 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators. ...
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... Figure 1-1. The pinouts for this device family are listed in Table 1-2. Like all Microchip PIC18 devices, members of the PIC18F1230/1330 family are available as both stan- dard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an “F” in the ...
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... Timers Power Control PWM Module Serial Communications 10-Bit Analog-to-Digital Module Resets (and Delays) Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set Packages 2009 Microchip Technology Inc. PIC18F1230/1330 PIC18F1230 DC – 40 MHz 4096 2048 256 128 17 Ports Channels Enhanced USART 4 Input Channels ...
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... PIC18F1230/1330 FIGURE 1-1: PIC18F1230/1330 (18-PIN) BLOCK DIAGRAM Table Pointer <2> 21 inc/dec logic PCLATU Address Latch Program Memory (4 Kbytes) PIC18F1230 (8 Kbytes) PIC18F1330 Data Latch 16 Table Latch 8 ROM Latch Instruction Register Instruction Decode & Control (2) OSC1 Power-up Timing (2) Generation OSC2 Oscillator Start-up Timer ...
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... TABLE 1-2: PIC18F1230/1330 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP, SSOP SOIC MCLR/V /RA5/FLTA MCLR V PP RA5 (1) FLTA RA7/OSC1/CLKI T1OSI/FLTA RA7 OSC1 CLKI (2) T1OSI (1) FLTA RA6/OSC2/CLKO T1OSO/T1CKI/AN3 RA6 OSC2 CLKO (2) T1OSO (2) TICKI AN3 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... PIC18F1230/1330 TABLE 1-2: PIC18F1230/1330 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP, SSOP SOIC RA0/AN0/INT0/KBI0 CMP0 RA0 AN0 INT0 KBI0 CMP0 RA1/AN1/INT1/KBI1 2 2 RA1 AN1 INT1 KBI1 RA2/TX/ RA2 TX CK RA3/RX/ RA3 RX DT RA4/T0CKI/AN2 REF RA4 T0CKI AN2 V + REF Legend: TTL = TTL compatible input ...
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... TABLE 1-2: PIC18F1230/1330 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP, SSOP SOIC RB0/PWM0 8 9 RB0 PWM0 RB1/PWM1 9 10 RB1 PWM1 RB2/INT2/KBI2/CMP2 T1OSO/T1CKI RB2 INT2 KBI2 CMP2 (2) T1OSO (2) T1CKI RB3/INT3/KBI3/CMP1 T1OSI RB3 INT3 KBI3 CMP1 (2) T1OSI RB4/PWM2 10 11 RB4 PWM2 ...
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... PIC18F1230/1330 TABLE 1-2: PIC18F1230/1330 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP, SSOP SOIC — — Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. Note 1: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX CONFIG3H ...
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... GUIDELINES FOR GETTING STARTED WITH PIC18F MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC18F1230/1330 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All V and V ...
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... PIC18F1230/1330 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher ...
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... Overstress (EOS). Ensure that the MCLR pin V and V specifications are met 2009 Microchip Technology Inc. PIC18F1230/1330 2.4 ICSP Pins device The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible ...
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... PIC18F1230/1330 2.5 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0 ...
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... OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types PIC18F1230/1330 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL enabled 5 ...
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... PIC18F1230/1330 TABLE 3-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq kHz MHz MHz MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test ...
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... EXT C > EXT 2009 Microchip Technology Inc. PIC18F1230/1330 3.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator. This may be ...
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... PIC18F1230/1330 3.6 Internal Oscillator Block The PIC18F1230/1330 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC MHz clock source, which can be used to directly drive the device clock ...
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... OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment OSCTUNE to increase the clock frequency. 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘ ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F1230/1330 devices are shown in Figure 3-8. See Section 20.0 “Special Features of the CPU” for Configuration register details. ...
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... Timer1 oscillator starts. 3.7.2 OSCILLATOR TRANSITIONS PIC18F1230/1330 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... PIC18F1230/1330 REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 IDLEN IRCF2 IRCF1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction ...
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... See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset. Note: 2009 Microchip Technology Inc. PIC18F1230/1330 time clock. Other features may be operating that do not require a device clock source (i.e., INTx pins and others). Peripherals that may add significant current consumption are listed in Section 23.0 “ ...
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... PIC18F1230/1330 NOTES: DS39758D-page 30 2009 Microchip Technology Inc. ...
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... POWER-MANAGED MODES PIC18F1230/1330 devices offer a total of seven operating modes for more efficient management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • Run modes • Idle modes • ...
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... PIC18F1230/1330 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. 2009 Microchip Technology Inc. PIC18F1230/1330 n-1 n (1) ...
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... PIC18F1230/1330 If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, ...
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... Sleep Mode The power-managed Sleep mode in the PIC18F1230/ 1330 devices is identical to the legacy Sleep mode offered in all other PIC devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared ...
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... PIC18F1230/1330 4.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. 2009 Microchip Technology Inc. PIC18F1230/1330 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution ...
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... PIC18F1230/1330 4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped; and • the primary clock source is not any of the LP, XT HSPLL modes ...
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... RESET The PIC18F1230/1330 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F1230/1330 REGISTER 5-1: RCON: RESET CONTROL REGISTER (1) R/W-0 R/W-1 U-0 IPEN SBOREN — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) ...
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... The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F1230/1330 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.1 “PORTA, TRISA and LATA Registers” ...
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... PIC18F1230/1330 5.4 Brown-out Reset (BOR) PIC18F1230/1330 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 5-1. The BOR threshold is set by the BORV1:BORV0 bits. ...
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... Oscillator Start-up Timer (OST) • PLL Lock Time-out 5.5.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of PIC18F1230/1330 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in Reset ...
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... PIC18F1230/1330 FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET T = 1024 clock cycles. Note: OST max. First three stages of the PWRT timer. T PLL 2009 Microchip Technology Inc. PIC18F1230/1330 , V RISE > PWRT T OST T PWRT T OST T PLL ...
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... PIC18F1230/1330 5.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When 5: not enabled as PORTA pins, they are disabled and read as ‘0’. Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. 6: 2009 Microchip Technology Inc. PIC18F1230/1330 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset RESET Instruction, ...
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... PIC18F1230/1330 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices INDF2 1230 1330 POSTINC2 1230 1330 POSTDEC2 1230 1330 PREINC2 1230 1330 PLUSW2 1230 1330 FSR2H 1230 1330 FSR2L 1230 1330 STATUS 1230 1330 TMR0H 1230 1330 TMR0L 1230 ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When 5: not enabled as PORTA pins, they are disabled and read as ‘0’. Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. 6: 2009 Microchip Technology Inc. PIC18F1230/1330 MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset RESET Instruction, ...
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... PIC18F1230/1330 TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices SEVTCMPH 1230 1330 PWMCON0 1230 1330 PWMCON1 1230 1330 DTCON 1230 1330 OVDCOND 1230 1330 OVDCONS 1230 1330 PORTB 1230 1330 PORTA 1230 1330 Legend unchanged unknown unimplemented bit, read as ‘0’ value depends on condition One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up) ...
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... NOP instruction). The PIC18F1230 has 4 Kbytes of Flash memory and can store up to 2,048 single-word instructions. The PIC18F1330 has 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. ...
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... PIC18F1230/1330 6.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
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... Bit 7 and bit 6 are cleared by user software POR. Note 1: 2009 Microchip Technology Inc. PIC18F1230/1330 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... PIC18F1230/1330 6.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 2009 Microchip Technology Inc. PIC18F1230/1330 6.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... PIC18F1230/1330 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction ...
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... RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; PIC18F1230/ 1330 devices implement 1 bank. Figure 6-5 shows the data memory organization for the PIC18F1230/1330 devices ...
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... PIC18F1230/1330 FIGURE 6-5: DATA MEMORY MAP FOR PIC18F1230/1330 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh = 0001 Bank 1110 Bank 14 00h = 1111 Bank 15 FFh DS39758D-page 58 Data Memory Map 000h Access RAM 07Fh 080h GPR 0FFh Unused Read ‘00h’ EFFh Unused F00h Read ‘00h’ ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, 2009 Microchip Technology Inc. PIC18F1230/1330 7 Data Memory 1 000h ...
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... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these registers is given in Table 6-1 and Table 6-2. TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F1230/1330 DEVICES Address Name Address FFFh ...
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... TABLE 6-2: REGISTER FILE SUMMARY (PIC18F1230/1330) File Name Bit 7 Bit 6 Bit 5 TOSU — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) (5) (5) STKPTR STKFUL STKUNF PCLATU — — PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... PIC18F1230/1330 TABLE 6-2: REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 STATUS — — TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T016BIT T0CS OSCCON IDLEN IRCF2 IRCF1 LVDCON — — IRVST WDTCON — — ...
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... TABLE 6-2: REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 PTMRL PWM Time Base Register (lower 8 bits) PTMRH — — PTPERL PWM Time Base Period Register (lower 8 bits) PTPERH — — TRISB PORTB Data Direction Control Register TRISA TRISA7 ...
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... PIC18F1230/1330 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruc- tion that affects the Z, DC bits, the results of the instruction are not written ...
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... Bank (Section 6.3.2 “Access Bank”) as the data source for the instruction. 2009 Microchip Technology Inc. PIC18F1230/1330 The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 6.3.1 “Bank Select Register (BSR)”) are used with the address to determine the complete 12-bit address of the register. When ‘ ...
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... PIC18F1230/1330 6.4.3.1 FSR Registers and the INDF Operand At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion ...
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... Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged. 2009 Microchip Technology Inc. PIC18F1230/1330 6.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair within Access RAM ...
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... PIC18F1230/1330 FIGURE 6-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When ‘a’ and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh ...
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... F80h by using the BSR. FFFh 2009 Microchip Technology Inc. PIC18F1230/1330 Remapping of the Access Bank applies only to operations using the Indexed Literal Offset Addressing mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. ...
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... PIC18F1230/1330 NOTES: DS39758D-page 70 2009 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 2009 Microchip Technology Inc. PIC18F1230/1330 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... PIC18F1230/1330 FIGURE 7-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 8 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”. ...
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... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error Note 1: condition. 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-x R/W-0 (1) FREE ...
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... PIC18F1230/1330 7.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
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... MOVF TABLAT, W MOVWF WORD_ODD 2009 Microchip Technology Inc. PIC18F1230/1330 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 7-4 shows the interface between the internal program memory and the TABLAT ...
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... PIC18F1230/1330 7.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
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... CFGS bit to access program memory; • set WREN to enable byte writes. 2009 Microchip Technology Inc. PIC18F1230/1330 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer ...
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... PIC18F1230/1330 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'88 MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER BRA READ_BLOCK ...
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... PIE2 OSCFIE — — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Legend: 2009 Microchip Technology Inc. PIC18F1230/1330 ; point to Flash program memory ; access Flash program memory ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ...
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... PIC18F1230/1330 NOTES: DS39758D-page 80 2009 Microchip Technology Inc. ...
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... EEADR Register The EEPROM Address register can address 256 bytes of data EEPROM. 2009 Microchip Technology Inc. PIC18F1230/1330 8.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same range. The data ...
Page 82
... PIC18F1230/1330 REGISTER 8-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 EEPGD CFGS — bit Settable bit Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory ...
Page 83
... SLEEP BCF EECON1, WREN 2009 Microchip Technology Inc. PIC18F1230/1330 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
Page 84
... PIC18F1230/1330 8.7 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 20.0 “ ...
Page 85
... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2009 Microchip Technology Inc. PIC18F1230/1330 EXAMPLE 9- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 9- SIGNED MULTIPLY ...
Page 86
... PIC18F1230/1330 Example 9-3 shows the sequence unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 9- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0= ARG1H:ARG1L ARG2H:ARG2L = (ARG1H ARG2H (ARG1H ARG2L (ARG1L ARG2H 2 ...
Page 87
... PORTA pin an output (i.e., put the contents of the output latch on the selected pin). 2009 Microchip Technology Inc. PIC18F1230/1330 Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Output Latch (LATA) register is also memory mapped ...
Page 88
... PIC18F1230/1330 TABLE 10-1: PORTA I/O SUMMARY TRIS Pin Function Setting RA0/AN0/INT0/ RA0 0 KBI0/CMP0 1 AN0 1 INT0 1 KBI0 1 CMP0 1 RA1/AN1/INT1/ RA1 0 KBI1 1 AN1 1 INT1 1 KBI1 1 RA2/TX/CK RA2 RA3/RX/DT RA3 RA4/T0CKI/AN2/ RA4 REF 1 T0CKI 1 AN2 REF 1 MCLR/V /RA5/ MCLR PP 1 FLTA RA5 1 (1) FLTA ...
Page 89
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator Note 1: configuration; otherwise, they are read as ‘0’. 2009 Microchip Technology Inc. PIC18F1230/1330 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 90
... PIC18F1230/1330 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 91
... Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default Note 1: when PBADEN is set and digital inputs when PBADEN is cleared. Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H. 2: 2009 Microchip Technology Inc. PIC18F1230/1330 I/O I/O Type O DIG LATB< ...
Page 92
... PIC18F1230/1330 TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB PORTB Output Latch Register (Read and Write to Data Latch) TRISB PORTB Data Direction Control Register INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP ...
Page 93
... INTERRUPTS The PIC18F1230/1330 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...
Page 94
... PIC18F1230/1330 FIGURE 11-1: PIC18 INTERRUPT LOGIC Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit ADIF ADIE ADIP From Power Control PWM PTIF Interrupt Logic PTIE PTIP Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation Peripheral Interrupt Flag bit ...
Page 95
... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and Note 1: allow the bit to be cleared. 2009 Microchip Technology Inc. PIC18F1230/1330 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 96
... PIC18F1230/1330 REGISTER 11-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 97
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding Note: enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-0 R/W-0 INT2IE ...
Page 98
... PIC18F1230/1330 11.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2 and PIR3). REGISTER 11-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 99
... PWM time base matched the value in PTPER register. Interrupt is issued according to the postscaler settings. PTIF must be cleared in software PWM time base has not matched the value in PTPER register bit 3-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 U-0 R/W-0 EEIF — ...
Page 100
... PIC18F1230/1330 11.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2 and PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts ...
Page 101
... Unimplemented: Read as ‘0’ bit 4 PTIE: PWM Time Base Interrupt Enable bit 1 = PWM enabled 0 = PWM disabled bit 3-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 U-0 R/W-0 EEIE — LVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 102
... PIC18F1230/1330 11.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 103
... Unimplemented: Read as ‘0’ bit 4 PTIP: PWM Time Base Interrupt Priority bit 1 = High priority 0 = Low priority bit 3-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-1 U-0 R/W-1 EEIP — LVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 104
... PIC18F1230/1330 11.5 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. REGISTER 11-13: RCON: RESET CONTROL REGISTER (1) R/W-0 ...
Page 105
... BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2009 Microchip Technology Inc. PIC18F1230/1330 11.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
Page 106
... PIC18F1230/1330 NOTES: DS39758D-page 106 2009 Microchip Technology Inc. ...
Page 107
... Prescale value 000 = 1:2 Prescale value 2009 Microchip Technology Inc. PIC18F1230/1330 Figure 12-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 12-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 12- readable and writable register that controls all the aspects of Timer0, including the prescale selection ...
Page 108
... PIC18F1230/1330 FIGURE 12-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE F /4 OSC 0 T0CKI pin 1 T0SE T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. FIGURE 12-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE F /4 OSC 0 T0CKI pin 1 Programmable Prescaler ...
Page 109
... Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0. RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in CONFIG1H. Note 1: 2009 Microchip Technology Inc. PIC18F1230/1330 12.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “ ...
Page 110
... PIC18F1230/1330 NOTES: DS39758D-page 110 2009 Microchip Technology Inc. ...
Page 111
... Stops Timer1 Note 1: Placement of T1OSI and T1OSO/T1CKI depends on the value of the Configuration bit, T1OSCMX, of CONFIG3H. 2009 Microchip Technology Inc. PIC18F1230/1330 Register 13-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 112
... PIC18F1230/1330 13.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the Clock Select bit, TMR1CS (T1CON<1>). FIGURE 13-1: TIMER1 BLOCK DIAGRAM TMR1IF Overflow TMR1 Interrupt Flag Bit TMR1H T1OSC ...
Page 113
... Capacitor values are for design guidance only. 2009 Microchip Technology Inc. PIC18F1230/1330 13.2.1 USING TIMER1 AS A CLOCK SOURCE The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the System Clock Select bits, SCS1:SCS0 (OSCCON<1:0>), to ‘ ...
Page 114
... PIC18F1230/1330 13.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 interrupt enable bit, TMR1IE (PIE1<0>). ...
Page 115
... T1CON RD16 T1RUN Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2009 Microchip Technology Inc. PIC18F1230/1330 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ...
Page 116
... PIC18F1230/1330 NOTES: DS39758D-page 116 2009 Microchip Technology Inc. ...
Page 117
... PWM outputs disable feature sets PWM outputs to their inactive state when in Debug mode. The Power Control PWM module supports three PWM generators and six output channels on PIC18F1230/ 1330 devices. A simplified block diagram of the module is shown in Figure 14-1. Figure 14-2 and Figure 14-3 ...
Page 118
... PIC18F1230/1330 FIGURE 14-1: POWER CONTROL PWM MODULE BLOCK DIAGRAM Internal Data Bus 8 PWMCON0 8 PWMCON1 8 DTCON 8 FLTCONFIG 8 OVDCON<D/S> PTMR Comparator PTPER 8 PTPER Buffer 8 PTCONx Comparator SEVTDIR 8 SEVTCMP Note 1: Only PWM Generator 2 is shown in detail. The other generators are identical; their details are omitted for clarity. ...
Page 119
... In Complementary modes, the even PWM pins must always be the complement of the corresponding odd PWM pins. For example, PWM0 will be the complement of PWM1 and PWM2 will be the complement of PWM3. The dead-time generator 2009 Microchip Technology Inc. PIC18F1230/1330 V DD Dead-Band Generator V ...
Page 120
... PIC18F1230/1330 14.1 Control Registers The operation of the PWM module is controlled by a total of 20 registers. Eight of these are used to configure the features of the module: • PWM Timer Control Register 0 (PTCON0) • PWM Timer Control Register 1 (PTCON1) • PWM Control Register 0 (PWMCON0) • PWM Control Register 1 (PWMCON1) • ...
Page 121
... The PWM time base can be configured for four different modes of operation: • Free-Running mode • Single-Shot mode • Continuous Up/Down Count mode • Continuous Up/Down Count mode with interrupts for double updates 2009 Microchip Technology Inc. PIC18F1230/1330 PTMR Clock Timer Reset Up/Down Zero Match Timer Direction PTDIR ...
Page 122
... PIC18F1230/1330 REGISTER 14-1: PTCON0: PWM TIMER CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 PTOPS3 PTOPS2 PTOPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 PTOPS3:PTOPS0: PWM Time Base Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale ...
Page 123
... For PMOD2 PWM I/O pin pair (PWM4, PWM5 the Independent mode 0 = PWM I/O pin pair (PWM4, PWM5 the Complementary mode Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. Note 1: 2009 Microchip Technology Inc. PIC18F1230/1330 (1) (1) R/W-1 U-0 R/W-0 PWMEN0 — ...
Page 124
... PIC18F1230/1330 REGISTER 14-4: PWMCON1: PWM CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 SEVOPS3 SEVOPS2 SEVOPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 SEVOPS3:SEVOPS0: PWM Special Event Trigger Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale ...
Page 125
... Write to the PTCON (PTCON0 or PTCON1) register • Any device Reset The PTMR register is not cleared when Note: PTCONx is written. 2009 Microchip Technology Inc. PIC18F1230/1330 Table 14-1 shows the minimum PWM frequencies that can be generated with the PWM time base and the prescaler. An operating ...
Page 126
... PIC18F1230/1330 FIGURE 14-5: PWM TIME BASE INTERRUPT TIMING, FREE-RUNNING MODE A: PRESCALER = 1 OSC PTMR FFEh PTMR_INT_REQ PTIF bit B: PRESCALER = 1 PTMR FFEh PTMR_INT_REQ PTIF bit Note 1: PWM Time Base Period register, PTPER, is loaded with the value FFFh for this example. 14.4.2 INTERRUPTS IN SINGLE-SHOT ...
Page 127
... PWM TIME BASE INTERRUPTS, CONTINUOUS UP/DOWN COUNT MODE PRESCALER = 1 OSC 002h PTMR PTDIR bit PTMR_INT_REQ 1 1 PTIF bit PRESCALER = 1 PTMR 002h PTDIR bit 1 1 PTMR_INT_REQ PTIF bit Note 1: Interrupt flag bit, PTIF, is sampled here (every Q1). 2009 Microchip Technology Inc. PIC18F1230/1330 FFFh 000h FFFh 000h ...
Page 128
... PIC18F1230/1330 14.4.4 INTERRUPTS IN DOUBLE UPDATE MODE This mode is available in Continuous Up/Down Count mode. In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero and each time the PTMR matches the PTPER register. Figure 14-8 shows the interrupts in Continuous Up/Down Count mode with double updates ...
Page 129
... The PWM frequency is the inverse of period; or EQUATION 14-3: PWM FREQUENCY 1 PWM Frequency = PWM Period 2009 Microchip Technology Inc. PIC18F1230/1330 The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula: EQUATION 14-4: PWM RESOLUTION F ...
Page 130
... PIC18F1230/1330 FIGURE 14-9: PWM PERIOD BUFFER UPDATES IN FREE-RUNNING MODE New PTPER Value = 007 Old PTPER Value = 004 1 0 FIGURE 14-10: PWM PERIOD BUFFER UPDATES IN CONTINUOUS UP/DOWN COUNT MODES New PTPER Value = 007 Old PTPER Value = 004 1 0 DS39758D-page 130 Period Value Loaded from PTPER Buffer Register ...
Page 131
... duty cycle match occurs duty cycle match occurs on Q4 2009 Microchip Technology Inc. PIC18F1230/1330 PTMR and the lower 2 bits are equal to Q1, Q2 Q4, depending on the lower two bits of the PDCx (when the prescaler is 1:1 or PTCKPS<1:0> = 00) ...
Page 132
... PIC18F1230/1330 14.6.2 DUTY CYCLE REGISTER BUFFERS The three PWM Duty Cycle registers are double- buffered to allow glitchless updates of the PWM outputs. For each duty cycle block, there is a Duty Cycle Buffer register that is accessible by the user and a second Duty Cycle register that holds the actual compare value used in the present PWM period ...
Page 133
... Start of First PWM Period 2009 Microchip Technology Inc. PIC18F1230/1330 Duty Cycle Value Loaded from Buffer Register New Values Written to Duty Cycle Buffer inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to or greater than the value in the PTPER register ...
Page 134
... PIC18F1230/1330 14.6.5 COMPLEMENTARY PWM OPERATION The Complementary mode of PWM operation is useful to drive one or more power switches in half-bridge configuration, as shown in Figure 14-16. This inverter topology is typical for a 3-phase induction motor, brushless DC motor or 3-phase Uninterruptible Power Supply (UPS) control applications. Each upper/lower power switch pair is fed by a complementary PWM signal ...
Page 135
... PDC1 Compare Output PWM1 PWM0 2009 Microchip Technology Inc. PIC18F1230/1330 14.7.1 DEAD-TIME INSERTION Each complementary output pair for the PWM module has a 6-bit down counter used to produce the dead- time insertion. As shown in Figure 14-17, each dead- time unit has a rising and falling edge detector connected to the duty cycle comparison output ...
Page 136
... PIC18F1230/1330 REGISTER 14-5: DTCON: DEAD-TIME CONTROL REGISTER R/W-0 R/W-0 R/W-0 DTPS1 DTPS0 DT5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 DTPS1:DTPS0: Dead-Time Unit A Prescale Select bits 11 = Clock source for dead-time unit Clock source for dead-time unit is F ...
Page 137
... F /16 OSC 2009 Microchip Technology Inc. PIC18F1230/1330 14.7.4 DEAD-TIME DISTORTION Note 1: For small PWM duty cycles, the ratio of dead time to the active PWM time may become large. In this case, the inserted dead time will introduce distortion into waveforms produced by the PWM mod- ule ...
Page 138
... PIC18F1230/1330 14.8.2 PWM CHANNEL OVERRIDE PWM output may be manually overridden for each PWM channel by using the appropriate bits in the OVDCOND and OVDCONS registers. The user may select the following signal output options for each PWM output pin operating in the Independent PWM mode: • ...
Page 139
... Odd override bit is activated which causes the even PWM to deactivate. 3. Dead-time insertion. 4. Odd PWM activated after the dead time. 5. Odd override bit is deactivated which causes the odd PWM to deactivate. 6. Dead-time insertion. 7. Even PWM is activated after the dead time. 2009 Microchip Technology Inc. PIC18F1230/1330 DS39758D-page 139 ...
Page 140
... PIC18F1230/1330 14.10.3 OUTPUT OVERRIDE EXAMPLES Figure 14-21 shows an example of a waveform that might be generated using the PWM output override feature. The figure shows a six-step commutation sequence for a BLDC motor. The motor is driven through a 3-phase inverter as shown in Figure 14-16. When the appropriate rotor position is detected, the PWM outputs are switched to the next commutation state in the sequence ...
Page 141
... PWM4 PWM3 PWM2 PWM1 PWM0 2009 Microchip Technology Inc. PIC18F1230/1330 14.11 PWM Output and Polarity Control There are three device Configuration bits associated with the PWM module that provide PWM output pin 5 6 control defined in the CONFIG3L register. They are: • ...
Page 142
... PIC18F1230/1330 FIGURE 14-23: PWM I/O PIN BLOCK DIAGRAM PWM Signal from Module PWM Pin Enable Data Bus WR PORT Data Latch WR TRIS TRIS Latch RD TRIS RD PORT I/O pin has protection diodes to V Note: 14.11.3 PWM OUTPUT PIN RESET STATES The PWMPIN Configuration bit determines the PWM output pins to be PWM output pins, or digital I/O pins, after the device comes out of Reset ...
Page 143
... FLTAEN: Fault A Enable bit 1 = Enable Fault Disable Fault A 2009 Microchip Technology Inc. PIC18F1230/1330 14.12.3 PWM OUTPUTS WHILE IN FAULT CONDITION While in the Fault state (i.e., FLTA input is active), the PWM output signals are driven into their inactive states ...
Page 144
... PIC18F1230/1330 14.13 PWM Update Lockout For a complex PWM application, the user may need to write up to four Duty Cycle registers and the PWM Time Base Period Register, PTPER given time. In some applications important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module ...
Page 145
... Shaded cells are not used with the Power Control PWM. Legend: Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to. Note 1: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit. 2: 2009 Microchip Technology Inc. PIC18F1230/1330 Bit 5 Bit 4 Bit 3 TMR0IE INT0IE RBIE TMR0IF — ...
Page 146
... PIC18F1230/1330 NOTES: DS39758D-page 146 2009 Microchip Technology Inc. ...
Page 147
... Synchronous – Master (half-duplex) with Selectable Clock Polarity • Synchronous – Slave (half-duplex) with Selectable Clock Polarity 2009 Microchip Technology Inc. PIC18F1230/1330 The pins of the Enhanced USART are multiplexed with PORTA. In order to configure RA2/TX/CK and RA3/RX/ EUSART: • bit SPEN (RCSTA<7>) must be set (= 1) • ...
Page 148
... PIC18F1230/1330 REGISTER 15-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 CSRC TX9 TXEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode Master mode (clock generated internally from BRG) ...
Page 149
... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-0 R-0 CREN ADDEN FERR U = Unimplemented bit, read as ‘ ...
Page 150
... PIC18F1230/1330 REGISTER 15-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 ABDOVF RCIDL RXDTP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) ...
Page 151
... Legend Don’t care value of SPBRGH:SPBRG register pair 2009 Microchip Technology Inc. PIC18F1230/1330 Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. ...
Page 152
... PIC18F1230/1330 EXAMPLE 15-1: CALCULATING BAUD RATE ERROR For a device with MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: OSC Desired Baud Rate = F /(64 ([SPBRGH:SPBRG] + 1)) OSC Solving for SPBRGH:SPBRG ((F /Desired Baud Rate)/64) – 1 OSC = ((16000000/9600)/64) – [25.042 Calculated Baud Rate = 16000000/(64 (25 + 1)) ...
Page 153
... Microchip Technology Inc. PIC18F1230/1330 SYNC = 0, BRGH = 0, BRG16 = 20.000 MHz F = 10.000 MHz OSC OSC SPBRG Actual % Rate value Rate Error Error (K) (decimal) (K) — — ...
Page 154
... PIC18F1230/1330 TABLE 15-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) BAUD F = 40.000 MHz OSC RATE Actual SPBRG Actual (K) % Rate value Error (K) (decimal) 0.3 0.300 0.00 8332 1.2 1.200 0.02 2082 2.4 2.402 0.06 1040 9.6 9.615 0.16 259 19.2 19.231 0.16 129 19 ...
Page 155
... RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. 2009 Microchip Technology Inc. PIC18F1230/1330 Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. ...
Page 156
... PIC18F1230/1330 FIGURE 15-1: AUTOMATIC BAUD RATE CALCULATION BRG Value XXXXh 0000h RX pin BRG Clock Set by User ABDEN bit RCIF bit (interrupt) Read RCREG SPBRG SPBRGH Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. FIGURE 15-2: ...
Page 157
... Asynchronous Receiver • Auto-Wake-up on Sync Break Character • 12-Bit Break Character Transmit • Auto-Baud Rate Detection 2009 Microchip Technology Inc. PIC18F1230/1330 15.2.1 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 15-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR) ...
Page 158
... PIC18F1230/1330 FIGURE 15-3: EUSART TRANSMIT BLOCK DIAGRAM TXIF TXIE Interrupt Baud Rate CLK TXEN BRG16 SPBRGH SPBRG Baud Rate Generator FIGURE 15-4: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX (pin) Start bit TXIF bit (Transmit Buffer Reg. Empty Flag) ...
Page 159
... EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. 2009 Microchip Technology Inc. PIC18F1230/1330 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE ...
Page 160
... PIC18F1230/1330 15.2.2 EUSART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 15-6. The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate ...
Page 161
... CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN/J2602 protocol.) 2009 Microchip Technology Inc. PIC18F1230/1330 Start Stop bit 7/8 bit 7/8 ...
Page 162
... PIC18F1230/1330 15.2.4.1 Special Considerations Using Auto-Wake-up Since auto-wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the Stop bit may signal a false End-of-Character and cause data or framing errors. To work properly, therefore, the initial characters in the transmission must be all ‘ ...
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... Reg. Empty Flag) SENDB Sampled Here SENDB (Transmit Shift Reg. Empty Flag) 2009 Microchip Technology Inc. PIC18F1230/1330 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. ...
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... PIC18F1230/1330 15.3 EUSART Synchronous Master Mode The Master mode indicates that the processor trans- mits the master clock on the CK line. The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time) ...
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... EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. 2009 Microchip Technology Inc. PIC18F1230/1330 bit 2 bit 0 bit 1 Bit 5 Bit 4 ...
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... PIC18F1230/1330 15.3.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RX pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received ...
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... SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. 2009 Microchip Technology Inc. PIC18F1230/1330 To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC ...
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... PIC18F1230/1330 15.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode ...
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... CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 4 inputs for the 18/20/28-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number in PIC18F1230/ 1330 devices. The module has five registers: • A/D Result Register High Byte (ADRESH) • ...
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... PIC18F1230/1330 REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4 VCFG0: Voltage Reference Configuration bit ( Positive reference for the A ...
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... OSC If the A/D F clock source is selected, a delay of one T Note 1: RC clock starts. This allows the SLEEP instruction to be executed before starting a conversion. 2009 Microchip Technology Inc. PIC18F1230/1330 R/W-0 R/W-0 R/W-0 ACQT1 ACQT0 ADCS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F1230/1330 The analog reference voltage is software selectable to the device’s positive supply voltage (V voltage level on the RA4/T0CKI/AN2/V The A/D Converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D Converter’s internal RC oscillator. ...
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... Sampling Switch C = Sample/Hold Capacitance (from DAC) HOLD R = Sampling Switch Resistance SS 2009 Microchip Technology Inc. PIC18F1230/1330 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt 6. Read A/D Result registers (ADRESH:ADRESL); ...
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... PIC18F1230/1330 16.1 Triggering A/D Conversions The A/D conversion can be triggered by setting the GO/ DONE bit. This bit can either be set manually by the programmer or by setting the SEVTEN bit of ADCON0. When the SEVTEN bit is set, the Special Event Trigger from the Power Control PWM module triggers the A/D conversion. For more information, see Section 14.14 “ ...
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... AD minimum T information). Table 16-1 shows the resultant T the device operating frequencies and the A/D clock source selected. ) Maximum Device Frequency AD PIC18F1230/1330 2.86 MHz 000 5.71 MHz 100 11.43 MHz 001 22.86 MHz 101 40.0 MHz 010 40 ...
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... PIC18F1230/1330 16.5 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device power-managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used in that mode ...
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... Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) 2009 Microchip Technology Inc. PIC18F1230/1330 After the A/D conversion is completed or aborted wait is required before the next acquisition can AD be started. After this wait, acquisition on the selected channel is automatically started. ...
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... PIC18F1230/1330 TABLE 16-2: REGISTERS ASSOCIATED WITH A/D OPERATION Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 — ADIF PIE1 — ADIE IPR1 — ADIP ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte ADCON0 SEVTEN — ADCON1 — ...
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... CMEN0: Comparator 0 Enable bit 1 = Comparator 0 is enabled 0 = Comparator 0 is disabled 2009 Microchip Technology Inc. PIC18F1230/1330 Section 18.0 Module”). The digital outputs are not available at the pin level and can only be read through the control register, CMCON (Register 17-1). CMCON also selects the comparator input ...
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... PIC18F1230/1330 17.1 Comparator Configuration For every analog comparator, there is a control bit called CMENx in the CMCON register. By setting the CMENx bit, the corresponding comparator can be enabled. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 23.0 “ ...
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... I LEAKAGE 2009 Microchip Technology Inc. PIC18F1230/1330 17.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 17-2. Since the analog pins are connected to a digital output, they have reverse biased diodes to V and V . The analog input, therefore, must be between ...
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... PIC18F1230/1330 TABLE 17-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Name Bit 7 Bit 6 CMCON C2OUT C1OUT CVRCON CVREN — INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 — ADIF PIE1 — ADIE IPR1 — ADIP (1) (1) PORTA RA7 RA6 (1) (1) LATA LATA7 LATA6 (1) (1) TRISA TRISA7 ...
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... REF RSRC CV ) RSRC 2009 Microchip Technology Inc. PIC18F1230/1330 The comparator reference supply voltage can come from either AV multiplexed with RA4 and AV selected by the CVRSS bit (CVRCON<4>). Additionally, the voltage reference can select the unscaled V REF bypassing the CV Figure 18-1 ...
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... PIC18F1230/1330 REGISTER 18-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 CVREN — CVRR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 CVREN: Comparator Voltage Reference Enable bit circuit powered on REF circuit powered down REF bit 6 Unimplemented: Read as ‘ ...
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... Section 23.0 “Electrical Characteristics”. TABLE 18-2: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Name Bit 7 Bit 6 CVRCON CVREN — CMCON C2OUT C1OUT Legend: Shaded cells are not used with the comparator voltage reference. 2009 Microchip Technology Inc. PIC18F1230/1330 8R CVR3:CVR0 Steps 18.3 Operation During Sleep ...
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... PIC18F1230/1330 NOTES: DS39758D-page 186 2009 Microchip Technology Inc. ...
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... LOW-VOLTAGE DETECT (LVD) PIC18F1230/1330 devices have a Low-Voltage Detect module (LVD). This is a programmable circuit that allows the user to specify the device voltage trip point. If the device experiences an excursion past the trip point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt ...
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... PIC18F1230/1330 The module is enabled by setting the LVDEN bit. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit and is used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set ...
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... Enable LVD IRVST Internal reference is stable 2009 Microchip Technology Inc. PIC18F1230/1330 Depending on the application, the LVD module does not need to be operating constantly. To decrease the current requirements, the LVD circuitry may only need to be enabled for short periods where the voltage is checked ...
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... PIC18F1230/1330 19.5 Applications In many applications, the ability to detect a drop below a particular threshold is desirable. For general battery applications, Figure 19-3 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage V , the LVD logic generates an interrupt at time T ...
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... Configurations”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F1230/1330 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits or software controlled (if configured as disabled). ...
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... PIC18F1230/1330 REGISTER 20-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 IESO FCMEN — bit 7 Legend Readable bit P = Programmable bit -n = Value when device is unprogrammed bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 ...
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... PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled See Section 23.1 “DC Characteristics” for the specifications. Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently 2: controlled. 2009 Microchip Technology Inc. PIC18F1230/1330 R/P-1 R/P-1 R/P-1 (1) (1) (2) BORV1 BORV0 BOREN1 U = Unimplemented bit, read as ‘ ...
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... PIC18F1230/1330 REGISTER 20-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 — — — bit 7 Legend Readable bit P = Programmable bit -n = Value when device is unprogrammed bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 ...
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... Polarity control bits, HPOL and LPOL, define PWM signal output active and inactive states, PWM states Note 1: generated by the Fault inputs or PWM manual override. When PWMPIN = 0, PWMEN<2:0> = 100. PWM output polarity is defined by HPOL and LPOL. 2: 2009 Microchip Technology Inc. PIC18F1230/1330 U-0 R/P-1 R/P-1 (1) (1) — ...
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... PIC18F1230/1330 REGISTER 20-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 MCLRE — — bit 7 Legend Readable bit P = Programmable bit -n = Value when device is unprogrammed bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled, RA5 input pin disabled 0 = RA5 input pin enabled, MCLR pin disabled bit 6-4 Unimplemented: Read as ‘ ...
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... BBSIZ<1:0>: Boot Block Size Select bits For PIC18F1330 device Boot Block size Boot Block size 01 = 512W Boot Block size 00 = 256W Boot Block size For PIC18F1230 device 512W Boot Block size 10 = 512W Boot Block size 01 = 512W Boot Block size 00 = 256W Boot Block size bit 3 Unimplemented: Maintain as ‘ ...
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... PIC18F1230/1330 REGISTER 20-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 — — — bit 7 Legend Readable bit C = Clearable bit -n = Value when device is unprogrammed bit 7-2 Unimplemented: Read as ‘0’ bit 1 CP1: Code Protection bit (Block 1 Code Memory Area) ...
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... Configuration registers are write-protected bit 4-0 Unimplemented: Read as ‘0’ This bit is read-only in normal execution mode; it can be written only in Program mode. Note 1: 2009 Microchip Technology Inc. PIC18F1230/1330 U-0 U-0 — — Unimplemented bit, read as ‘0’ Unchanged from programmed state ...
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... PIC18F1230/1330 REGISTER 20-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 — — — bit 7 Legend Readable bit C = Clearable bit -n = Value when device is unprogrammed bit 7-2 Unimplemented: Read as ‘0’ bit 1 EBTR1: Table Read Protection bit (Block 1 Code Memory Area) ...