PIC18F1230-I/SO Microchip Technology, PIC18F1230-I/SO Datasheet - Page 166

• Manufacturer Part Number: PIC18F1230-I/SO
• Description: IC PIC MCU FLASH 2KX16 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1230-I/SO

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Package: 18SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Interface Type: USART
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 2
• Processor Series: PIC18F
• Core: PIC
• Data Ram Size: 256 B
• Maximum Clock Frequency: 40 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• Height: 2.31 mm
• Length: 11.53 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1230/1330
15.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
FIGURE 15-13:
TABLE 15-8:
DS39758D-page 166
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON ABDOVF
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Name
RA2/TX/CK pin
If any error occurred, clear the error by clearing
bit, CREN.
If using interrupts, ensure that the GIE and PEIE bits
in the INTCON register (INTCON<7:6>) are set.
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud
rate.
RA3/RX/DT
(Interrupt)
CREN bit
bit SREN
SREN bit
(TXCKP)
RCIF bit
RXREG
Write to
Read
EUSART SYNCHRONOUS
MASTER RECEPTION
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
pin
GIE/GIEH PEIE/GIEL TMR0IE
Q2
CSRC
SPEN
Bit 7
‘0’
—
—
—
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 0
RXDTP
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
bit 2
TXCKP
INT0IE
CREN
SYNC
TXIE
TXIP
Bit 4
TXIF
bit 3
CMP2IE
CMP2IP
CMP2IF
ADDEN
SENDB
BRG16
RBIE
4.
5.
6.
7.
8.
9.
10. Interrupt flag bit, RCIF, will be set when reception
11. Read the RCSTA register to get the 9th bit (if
12. Read the 8-bit received data by reading the
Bit 3
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
Ensure bits, CREN and SREN, are clear.
If the signal from the CK pin is to be inverted, set
the TXCKP bit.
If interrupts are desired, set enable bit, RCIE.
If 9-bit reception is desired, set bit, RX9.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
enabled) and determine if any error occurred
during reception.
RCREG register.
bit 4
CMP1IE
CMP1IP
TMR0IF
CMP1IF
BRGH
FERR
Bit 2
—
bit 5
CMP0IE
CMP0IP
CMP0IF
INT0IF
OERR
TRMT
WUE
bit 6
Bit 1
 2009 Microchip Technology Inc.
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
Bit 0
RBIF
bit 7
Q1 Q2 Q3 Q4
on Page:
Values
Reset
47
49
49
49
48
48
48
48
48
48
‘0’