PIC18F1230-I/SO Microchip Technology, PIC18F1230-I/SO Datasheet - Page 79

• Manufacturer Part Number: PIC18F1230-I/SO
• Description: IC PIC MCU FLASH 2KX16 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1230-I/SO

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Package: 18SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Interface Type: USART
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 2
• Processor Series: PIC18F
• Core: PIC
• Data Ram Size: 256 B
• Maximum Clock Frequency: 40 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• Height: 2.31 mm
• Length: 11.53 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

EXAMPLE 7-3:
7.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed, if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out Reset
during normal operation, the user can check the
WRERR bit and rewrite the location(s) as needed.
TABLE 7-2:
 2009 Microchip Technology Inc.
TBLPTRU
TBPLTRH
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend:
PROGRAM_MEMORY
Name
Required
Sequence
— = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH
OSCFIP
OSCFIF
OSCFIE
EEPGD
Bit 7
—
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PEIE/GIEL
CFGS
Bit 6
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
—
—
—
—
TMR0IE
bit 21
Bit 5
—
—
—
—
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INT0IE
FREE
EEIP
EEIF
EEIE
Bit 4
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
WRERR
RBIE
Bit 3
—
—
—
7.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 20.0 “Special Features of the
CPU” for more detail.
7.6
See Section 20.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TMR0IF
Flash Program Operation During
Code Protection
PIC18F1230/1330
WREN
LVDIP
LVDIF
LVDIE
Bit 2
PROTECTION AGAINST
SPURIOUS WRITES
INT0IF
Bit 1
WR
—
—
—
Bit 0
RBIF
RD
—
—
—
DS39758D-page 79
Values on
Reset
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