PIC18F1230-I/SO Microchip Technology, PIC18F1230-I/SO Datasheet - Page 138

• Manufacturer Part Number: PIC18F1230-I/SO
• Description: IC PIC MCU FLASH 2KX16 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1230-I/SO

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Package: 18SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Interface Type: USART
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 2
• Processor Series: PIC18F
• Core: PIC
• Data Ram Size: 256 B
• Maximum Clock Frequency: 40 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• Height: 2.31 mm
• Length: 11.53 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1230/1330
14.8.2
PWM output may be manually overridden for each
PWM channel by using the appropriate bits in the
OVDCOND and OVDCONS registers. The user may
select the following signal output options for each PWM
output pin operating in the Independent PWM mode:
• I/O pin outputs PWM signal
• I/O pin inactive
• I/O pin active
Refer to Section 14.10 “PWM Output Override” for
details for all the override functions.
FIGURE 14-19:
14.9
The single-pulse PWM operation is available only in
Edge-Aligned mode. In this mode, the PWM module
will
operation is configured when the PTMOD1:PTMOD0
bits are set to ‘01’ in the PTCON0 register. This mode
of operation is useful for driving certain types of ECMs.
In Single-Pulse mode, the PWM I/O pin(s) are driven to
the active state when the PTEN bit is set. When the
PWM timer match with Duty Cycle register occurs, the
PWM I/O pin is driven to the inactive state. When the
PWM timer match with the PTPER register occurs, the
PTMR register is cleared, all active PWM I/O pins are
driven to the inactive state, the PTEN bit is cleared and
an interrupt is generated if the corresponding interrupt
bit is set.
14.10 PWM Output Override
The PWM output override bits allow the user to
manually drive the PWM I/O pins to specified logic
states, independent of the duty cycle comparison units.
The PWM override bits are useful when controlling
various types of ECMs, like a BLDC motor.
DS39758D-page 138
Note:
produce
Single-Pulse PWM Operation
PWM CHANNEL OVERRIDE
PTPER and PDCx values are held as they
are after the single-pulse output. To have
another cycle of single pulse, only PTEN
has to be enabled.
+V
single-pulse
PWM1
CENTER CONNECTED
LOAD
PWM0
Load
output.
Single-pulse
OVDCOND and OVDCONS registers are used to
define the PWM override options. The OVDCOND
register contains six bits, POVD5:POVD0, that
determine which PWM I/O pins will be overridden. The
OVDCONS register contains six bits, POUT5:POUT0,
that determine the state of the PWM I/O pins when a
particular output is overridden via the POVD bits.
The POVD bits are active-low control bits. When the
POVD bits are set, the corresponding POUT bit will
have no effect on the PWM output. In other words, the
pins corresponding to POVD bits that are set will have
the duty PWM cycle set by the PDCx registers. When
one of the POVD bits is cleared, the output on the
corresponding PWM I/O pin will be determined by the
state of the POUT bit. When a POUT bit is set, the
PWM pin will be driven to its active state. When the
POUT bit is cleared, the PWM pin will be driven to its
inactive state.
14.10.1
The even numbered PWM I/O pins have override
restrictions when a pair of PWM I/O pins are operating
in the Complementary mode (PMODx = 0). In
Complementary mode, if the even numbered pin is
driven active by clearing the corresponding POVD bit
and by setting the POUT bits in the OVDCOND and
OVDCONS registers, the output signal is forced to be
the complement of the odd numbered I/O pin in the pair
(see Figure 14-2 for details).
14.10.2
If the OSYNC bit in the PWMCON1 register is set, all
output overrides performed via the OVDCOND and
OVDCONS registers will be synchronized to the PWM
time base. Synchronous output overrides will occur on
the following conditions:
• When the PWM is in Edge-Aligned mode,
• When the PWM is in Center-Aligned mode,
synchronization occurs when PTMR is zero.
synchronization occurs when PTMR is zero and
when the value of PTMR matches PTPER.
Note 1: In the Complementary mode, the even
2: Dead time inserted in the PWM channels
COMPLEMENTARY OUTPUT MODE
OVERRIDE SYNCHRONIZATION
channel cannot be forced active by a
Fault or override event when the odd
channel is active. The even channel is
always the complement of the odd
channel, with dead-time inserted, before
the odd channel can be driven to its active
state as shown in Figure 14-20.
even when they are in Override mode.
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