PIC16F74-I/P Microchip Technology, PIC16F74-I/P Datasheet - Page 269

• Manufacturer Part Number: PIC16F74-I/P
• Description: IC MCU FLASH 4KX14 A/D 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F74-I/P

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC16F
• No. Of I/o's: 33
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 33
• Interface Type: I2C/SPI/USART
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Ram Size: 192 B
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.4.1.2
SDA
SCL
SSPIF
1997 Microchip Technology Inc.
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S
Reception
A7 A6 A5 A4 A3 A2 A1
1
2
Receiving Address
3
When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the
SSPSTAT register is cleared. The received address is loaded into the SSPBUF register.
When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An
overflow condition is defined as either the BF bit (SSPSTAT<0>) is set or the SSPOV bit
(SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer byte. The SSPIF flag bit must be cleared in
software, and the SSPSTAT register is used to determine the status of the byte.
Figure 16-8:
4
5
6
7
R/W=0
8
I
2
C Waveforms for Reception (7-bit Address)
ACK
9
D7
1
D6
2
SSPBUF register is read
Cleared in software
Receiving Data
D5
3
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
D1
7
D0
8
ACK
Section 16. BSSP
9
D7
1
D6
2
D5
Receiving Data
3
D4
4
ACK is not sent.
D3
5
D2
6
D1
7
DS31016A-page 16-19
D0
8
ACK
9
transfer
Bus Master
terminates
P
16