PIC16F74-I/P Microchip Technology, PIC16F74-I/P Datasheet - Page 348

IC MCU FLASH 4KX14 A/D 40DIP

PIC16F74-I/P

Manufacturer Part Number
PIC16F74-I/P
Description
IC MCU FLASH 4KX14 A/D 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F74-I/P

Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
33
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16F
No. Of I/o's
33
Ram Memory Size
192Byte
Cpu Speed
20MHz
No. Of Timers
3
Package
40PDIP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
33
Interface Type
I2C/SPI/USART
On-chip Adc
8-chx8-bit
Number Of Timers
3
Processor Series
PIC16F
Core
PIC
Data Ram Size
192 B
Maximum Clock Frequency
20 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCU
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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PICmicro MID-RANGE MCU FAMILY
DS31018A-page 18-12
RX (pin)
Rcv shift
reg
Rcv buffer reg
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
Start
Steps to follow when setting up an Asynchronous Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Figure 18-5:
bit
Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is
desired, set bit BRGH. (Subsection
Enable the asynchronous serial port by clearing the SYNC bit, and setting the SPEN bit.
If interrupts are desired, then set the RCIE, GIE and PEIE bits.
If 9-bit reception is desired, then set the RX9 bit.
Enable the reception by setting the CREN bit.
The RCIF flag bit will be set when reception is complete and an interrupt will be generated
if the RCIE bit was set.
Read the RCSTA register to get the ninth bit (if enabled) and determine if any error
occurred during reception.
Read the 8-bit received data by reading the RCREG register.
If any error occurred, clear the error by clearing the CREN bit.
bit0
bit1
Asynchronous Reception
bit7/8
Stop
bit
WORD 1
RCREG
Start
bit
18.3 “USART Baud Rate Generator (BRG)”
bit0
bit7/8
WORD 2
RCREG
Stop
bit
Start
bit
1997 Microchip Technology Inc.
bit7/8
Stop
bit
).

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