AT91SAM9XE128-QU Atmel, AT91SAM9XE128-QU Datasheet - Page 818

• Manufacturer Part Number: AT91SAM9XE128-QU
• Description: MCU ARM9 128K FLASH 208-PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE128-QU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

43.13 SDRAMC
43.13.1
43.13.2
818
AT91SAM9XE128/256/512 Preliminary
Timing Conditions
Timing Figures
SDRAMC timings are given in worst case conditions (1.65V/3.0V, 85°C).
Timings are given assuming a capacitance load on data, control and address pads:
Table 43-32. Capacitance Load on data, control and address pads
Table 43-33. Capacitance Load on SDCK pad
Table 43-34. SDRAM PC100 Characteristics
Table 43-35. SDRAM PC133 Characteristics
Supply
3.3V
1.8V
Supply
3.3V
1.8V
Parameter
SDRAM Controller Clock Frequency
Control/Address/Data In Setup
Control/Address/Data In Hold
Data Out Access time after SDCK rising
Data Out change time after SDCK rising
Parameter
SDRAM Controller Clock Frequency
Control/Address/Data In Setup
Control/Address/Data In Hold
Data Out Access time after SDCK rising
Data Out change time after SDCK rising
C
50pF
30 pF
C
10pF
10pF
LOAD
LOAD
Max
Max
(1)(2)
(1)(2)
(1)(2)
(1)(2)
3.3V Supply
3.3V Supply
Min
Min
1.5
0.8
3.0
2
1
3
3.3V Supply
3.3V Supply
Max
Max
100
133
5.4
6
6254C–ATARM–22-Jan-10
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns