AT91SAM9XE128-QU Atmel, AT91SAM9XE128-QU Datasheet - Page 830

• Manufacturer Part Number: AT91SAM9XE128-QU
• Description: MCU ARM9 128K FLASH 208-PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE128-QU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

43.15.4
Table 43-46. MCI Timings
830
Symbol
MCI
MCI
MCI
MCI
MCI
1
2
3
4
5
AT91SAM9XE128/256/512 Preliminary
MCI
Parameter
CLK frequency at Data transfer Mode
CLK frequency at Identification Mode
CLK Low time
CLK High time
CLK Rise time
CLK Fall time
CLK Low time
CLK High time
CLK Rise time
CLK Fall time
Input hold time
Input setup time
Output change after CLK rising
Output valid before CLK rising
The PDC interface block controls all data routing between the external data bus, internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine
that monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters
for the MMC/SD module (inner system) and the application (user programming).
These timings are given for a 25 pF load, corresponding to 1 MMC/SD Card.
Figure 43-20. MCI Timing Diagram
CMD_DAT Output
CMD_DAT Input
Bus Clock
5a
Valid Data
C = 100 pf
C = 250 pf
C = 100 pf
C = 100 pf
C = 100 pf
C = 100 pf
C = 250 pf
C = 250 pf
C = 250 pf
C = 250 pf
C = 25 pf
CLoad
3a
4a
5
3b
6a
Valid Data
Min
10
10
50
50
3
3
5
1
7
2
Valid Data
Valid Data
Max
400
25
20
20
10
10
50
50
6b
5b
4b
6254C–ATARM–22-Jan-10
Units
MHz
MHz
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns