P87C52SBPN,112 NXP Semiconductors, P87C52SBPN,112 Datasheet - Page 19
P87C52SBPN,112
Manufacturer Part Number
P87C52SBPN,112
Description
IC 80C51 MCU 8K OTP 40-DIP
Manufacturer
NXP Semiconductors
Series
87Cr
Datasheet
1.P87C52UBAA512.pdf
(38 pages)
Specifications of P87C52SBPN,112
Program Memory Type
OTP
Program Memory Size
8KB (8K x 8)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
8051
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR
Number Of I /o
32
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Processor Series
P87C5x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-1012-5
935253690112
P87C52SBPN
935253690112
P87C52SBPN
Philips Semiconductors
2000 Aug 07
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
BIT
IPH.7
IPH.6
IPH.5
IPH.4
IPH.3
IPH.2
IPH.1
IPH.0
IPH (B7H)
IP (0B8H)
SYMBOL
—
—
PT2
PS
PT1
PX1
PT0
PX0
SYMBOL
—
—
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
FUNCTION
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
FUNCTION
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit high.
Serial Port interrupt priority bit high.
Timer 1 interrupt priority bit high.
External interrupt 1 priority bit high.
Timer 0 interrupt priority bit high.
External interrupt 0 priority bit high.
—
—
7
7
—
—
6
6
PT2H
PT2
5
5
Figure 12. IPH Registers
Figure 11. IP Registers
PSH
PS
4
4
19
PT1H
PT1
3
3
PX1H
PX1
2
2
PT0H
80C51/87C51/80C52/87C52
PT0
1
1
SU00572
PX0H
PX0
0
0
SU01058
Product specification