ST62T20CB6 STMicroelectronics, ST62T20CB6 Datasheet - Page 12

IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part Number
ST62T20CB6
Description
IC MCU 8BIT OTP 4K 20 PDIP
Manufacturer
STMicroelectronics
Series
ST6r
Datasheet

Specifications of ST62T20CB6

Core Processor
ST6
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, WDT
Number Of I /o
12
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
ST6
No. Of I/o's
12
Ram Memory Size
64Byte
Cpu Speed
8MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ST62T2x
Core
ST6
Data Bus Width
8 bit
Data Ram Size
64 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
In Transition
Other names
497-2098-5
ST6208C/ST6209C/ST6210C/ST6220C
MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Legend:
x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s)
in the register.
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured
in input mode (refer to
4. Depending on device. See device summary on page 1.
12/104
1
Address
to 0D7h
to 0FEh
to 083h
0CAh
0CBh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0C8h
0C9h
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
0D8h
0D9h
0FFh
080h
0CCh
0CDh
0CEh
0CFh
Watchdog
I/O Ports
I/O Ports
I/O Ports
ADC
Timer1
Block
Timer
ROM
CPU
CPU
CPU
4)
Section 7 "I/O PORTS" on page 37
X,Y,V,W
DRA
DRB
DDRA
DDRB
IOR
DRWR
ORA
ORB
ADR
ADCR
PSCR
TCR
TSCR
WDGR
A
Register
Label
1) 2) 3)
1) 2) 3)
2)
2)
2)
2)
X,Y index registers
V,W short direct registers
Port A Data Register
Port B Data Register
Port A Direction Register
Port B Direction Register
Interrupt Option Register
Data ROM Window register
Port A Option Register
Port B Option Register
A/D Converter Data Register
A/D Converter Control Register
Timer 1 Prescaler Register
Timer 1 Downcounter Register
Timer 1 Status Control Register
Watchdog Register
Accumulator
Reserved (38 Bytes)
Reserved (2 Bytes)
Reserved (2 Bytes)
Reserved (2 Bytes)
Reserved (3 Bytes)
Reserved (2 bytes)
Register Name
for more details)
Status
Reset
0FFh
0FEh
7Fh
00h
00h
00h
00h
40h
00h
xxh
xxh
xxh
xxh
xxh
00h
00h
Write-only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Write-only
R/W
R/W
Read-only
Ro/Wo
R/W
R/W
R/W
Remarks

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