ST62T20CB6 STMicroelectronics, ST62T20CB6 Datasheet - Page 30

IC MCU 8BIT OTP 4K 20 PDIP

ST62T20CB6

Manufacturer Part Number
ST62T20CB6
Description
IC MCU 8BIT OTP 4K 20 PDIP
Manufacturer
STMicroelectronics
Series
ST6r
Datasheet

Specifications of ST62T20CB6

Core Processor
ST6
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, WDT
Number Of I /o
12
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
ST6
No. Of I/o's
12
Ram Memory Size
64Byte
Cpu Speed
8MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ST62T2x
Core
ST6
Data Bus Width
8 bit
Data Ram Size
64 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST622XC-KIT/110, ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
In Transition
Other names
497-2098-5
ST6208C/ST6209C/ST6210C/ST6220C
5.10 INTERRUPT HANDLING PROCEDURE
The interrupt procedure is very similar to a call pro-
cedure, in fact the user can consider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context and the time at which it occurred. As a re-
sult, the user should save all Data space registers
which may be used within the interrupt routines.
The following list summarizes the interrupt proce-
dure:
When an interrupt request occurs, the following
actions are performed by the MCU automatically:
– The core switches from the normal flags to the
– The PC contents are stored in the top level of the
– The normal interrupt lines are inhibited (NMI still
– The internal latch (if any) is cleared.
– The associated interrupt vector is loaded in the PC.
When an interrupt request occurs, the following
actions must be performed by the user software:
– User selected registers have to be saved within
– The source of the interrupt must be determined
– The RETI (RETurn from Interrupt) instruction
After the RETI instruction is executed, the MCU re-
turns to the main routine.
Caution: When a maskable interrupt occurs while
the ST6 core is in NORMAL mode and during the
execution of an “ldi IOR, 00h” instruction (disabling
all maskable interrupts): if the interrupt request oc-
curs during the first 3 cycles of the “ldi” instruction
(which is a 4-cycle instruction) the core will switch
to interrupt mode BUT the flags CN and ZN will
NOT switch to the interrupt pair CI and ZI.
5.10.1 Interrupt Response Time
This is defined as the time between the moment
when the Program Counter is loaded with the in-
terrupt vector and when the program has jump to
the interrupt subroutine and is ready to execute
the code. It depends on when the interrupt occurs
while the core is processing an instruction.
30/104
1
interrupt flags (or the NMI flags).
stack.
active).
the interrupt service routine (normally on a soft-
ware stack).
by polling the interrupt flags (if more than one
source is associated with the same vector).
must end the interrupt service routine.
Figure 18. Interrupt Processing Flow Chart
Table 7. Interrupt Response Time
One CPU cycle is 13 external clock cycles thus 11
CPU cycles = 11 x (13 /8M) = 17.875 µs with an 8
MHz external quartz.
*)
If a latch is present on the interrupt source line
Minimum
Maximum
YES
NO
AN INTERRUPT REQUEST
MASKABLE INTERRUPTS
AND INTERRUPT MASK?
THE INSTRUCTION
THE STACKED PC
NORMAL MODE?
NORMAL FLAGS
INSTRUCTION
INSTRUCTION
INSTRUCTION
IS THE CORE
IS THERE AN
ALREADY IN
EXECUTE
ENABLE
FETCH
A RETI?
SELECT
WAS
“POP”
6 CPU cycles
11 CPU cycles
YES
YES
NO
NO
MASKABLE INTERRUPT
INTERRUPT VECTOR
PC INTO THE STACK
INTERNAL LATCH
INTERRUPT FLAGS
LOAD PC FROM
PUSH THE
DISABLE
CLEAR
SELECT
*)

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