MC908SR12MFAE Freescale Semiconductor, MC908SR12MFAE Datasheet - Page 297

• Manufacturer Part Number: MC908SR12MFAE
• Description: IC MCU 12K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908SR12MFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, Temp Sensor
• Number Of I /o: 31
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.6.4 Repeated START Signal
17.6.5 STOP Signal
17.6.6 Arbitration Procedure
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
If the master receiver does not acknowledge the slave transmitter after
a byte has been transmitted, it means an “end of data” to the slave. The
slave should release the SDA line for the master to generate a STOP or
START signal.
As shown in
START signal without first generating a STOP to terminate the
communication. This is used by the master to communicate with another
slave or with the same slave in a different mode (transmit/receive mode)
without releasing the bus.
The master can terminate the communication by generating a STOP
signal to free the bus. However, the master may generate a START
signal followed by a calling command without first generating a STOP
signal. This is called repeat START. A STOP signal is defined as a low
to high transition of SDA while SCL is at logic high (see
The interface circuit is a multi-master system which allows more than
one master to be connected. If two or more masters try to control the bus
at the same time, a clock synchronization procedure determines the bus
clock. The clock low period is equal to the longest clock low period and
the clock high period is equal to the shortest one among the masters. A
data arbitration procedure determines the priority. A master will lose
arbitration if it transmits a logic 1 while another transmits a logic 0. The
losing master will immediately switch over to slave receive mode and
stops its data and clock outputs. The transition from master to slave will
not generate a STOP condition. Meanwhile a software bit will be set by
hardware to indicates loss of arbitration.
Multi-Master IIC Interface (MMIIC)
Figure
17-2, a repeated START signal is used to generate
Multi-Master IIC Interface (MMIIC)
Multi-Master IIC Bus Protocol
Figure
Data Sheet
17-2).
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