MC9S12XEP100CAG Freescale Semiconductor, MC9S12XEP100CAG Datasheet - Page 1074

• Manufacturer Part Number: MC9S12XEP100CAG
• Description: IC MCU 16BIT 1M FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24-ch x 12-bit
• Cpu Family: HCS12X
• Device Core Size: 16b
• Frequency (max): 50MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 25
• Operating Supply Voltage (typ): 1.8/2.8/5V
• Operating Supply Voltage (max): 1.98/2.9/5.5V
• Operating Supply Voltage (min): 1.72/2.7/3.13V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
27.4.3
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an EEE error or an ECC fault.
27.4.3.1
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the ERSEIF, PGMEIF, EPVIOLIF, ERSVIF1,
ERSVIF0, DFDIF and SFDIF flags in combination with the ERSEIE, PGMEIE, EPVIOLIE, ERSVIE1,
ERSVIE0, DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a
detailed description of the register bits involved, refer to
(FCNFG)”,
Status Register
The logic used for generating the Flash module interrupts is shown in
1074
Flash Command Complete
Flash EEE Erase Error
Flash EEE Program Error
Flash EEE Protection Violation
Flash EEE Error Type 1 Violation
Flash EEE Error Type 0 Violation
ECC Double Bit Fault on Flash Read
ECC Single Bit Fault on Flash Read
Section 27.3.2.6, “Flash Error Configuration Register
Interrupts
Description of Flash Interrupt Operation
Vector addresses and their relative interrupt priority are determined at the
MCU level.
(FSTAT)”, and
Interrupt Source
MC9S12XE-Family Reference Manual , Rev. 1.23
Section 27.3.2.8, “Flash Error Status Register
Table 27-79. Flash Interrupt Sources
(FERSTAT register)
(FERSTAT register)
(FERSTAT register)
(FERSTAT register)
(FERSTAT register)
(FERSTAT register)
(FERSTAT register)
(FSTAT register)
Interrupt Flag
PGMERIF
EPVIOLIF
ERSERIF
ERSVIF1
ERSVIF0
DFDIF
SFDIF
CCIF
NOTE
Section 27.3.2.5, “Flash Configuration Register
(FERCNFG register)
(FERCNFG register)
(FERCNFG register)
(FERCNFG register)
(FERCNFG register)
(FERCNFG register)
(FERCNFG register)
(FCNFG register)
(FERCNFG)”,
Local Enable
PGMERIE
EPVIOLIE
ERSERIE
ERSVIE1
ERSVIE0
DFDIE
SFDIE
CCIE
Figure
27-27.
(FERSTAT)”.
Section 27.3.2.7, “Flash
Freescale Semiconductor
Global (CCR)
Mask
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit