MC9S12XEP100CAG Freescale Semiconductor, MC9S12XEP100CAG Datasheet - Page 257
![IC MCU 16BIT 1M FLASH 144-LQFP](/photos/12/21/122161/mc9s12xep100cag_sml.jpg)
MC9S12XEP100CAG
Manufacturer Part Number
MC9S12XEP100CAG
Description
IC MCU 16BIT 1M FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEP100CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
119
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
24-ch x 12-bit
Cpu Family
HCS12X
Device Core Size
16b
Frequency (max)
50MHz
Total Internal Ram Size
64KB
# I/os (max)
119
Number Of Timers - General Purpose
25
Operating Supply Voltage (typ)
1.8/2.8/5V
Operating Supply Voltage (max)
1.98/2.9/5.5V
Operating Supply Voltage (min)
1.72/2.7/3.13V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Package
144LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XEP100CAG
Manufacturer:
FREESCAL
Quantity:
244
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Part Number:
MC9S12XEP100CAG
Manufacturer:
Freescale Semiconductor
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5.4.3
All read and write accesses to PRR addresses take two bus clock cycles independent of the operating mode.
If writing to these addresses in emulation modes, the access is directed to both, the internal register and
the external resource while reads will be treated external.
The XEBI control registers also belong to this category.
5.4.4
In order to allow fast internal bus cycles to coexist in a system with slower external resources, the XEBI
supports stretched external bus accesses (wait states) for each external address range related to one of the
4 chip select lines individually.
This feature is available in normal expanded mode and emulation expanded mode for accesses to all
external addresses except emulation memory and PRR. In these cases the fixed access times are 1 or 2
cycles, respectively.
Stretched accesses are controlled by:
The EXSTRx[2:0] control bits can be programmed for generation of a fixed number of 1 to 8 stretch
cycles. If the external wait feature is enabled, the minimum number of additional stretch cycles is 2. An
arbitrary amount of stretch cycles can be added using the EWAIT input.
EWAIT needs to be asserted at least for a minimal specified time window within an external access cycle
for the internal logic to detect it and add a cycle (refer to electrical characteristics). Holding it for additional
cycles will cause the external bus access to be stretched accordingly.
Write accesses are stretched by holding the initiator in its current state for additional cycles as programmed
and controlled by external wait after the data have been driven out on the external bus. This results in an
extension of time the bus signals and the related control signals are valid externally.
Read data are not captured by the system in normal expanded mode until the specified setup time before
the RE rising edge.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
1. EXSTR1[2:0] and EXSTR0[2:0] bits in the EBICTL1 register configuring a fixed amount of
2. Activation of the external wait feature for each CSx line MMCCTL0 register
3. Assertion of the external EWAIT signal when at least one CSx line is configured for EWAIT
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
RW
stretch cycles individually for each CSx line in MMCCTL0
Accesses to Port Replacement Registers
Stretched External Bus Accesses
Table 5-18. Interleaved Read-Write-Read Accesses (1 Cycle) (continued)
...
...
...
...
...
...
MC9S12XE-Family Reference Manual Rev. 1.23
addr 0
high
?
?
1
iqstat -1
acc 0
low
?
1
z
z
addr 1
data 0
high
0
z
iqstat 0
acc 1
ivd 0
low
Chapter 5 External Bus Interface (S12XEBIV4)
0
(write) data 1
(write) data 1
addr 2
high
1
iqstat 1
acc 2
low
x
z
z
1
...
...
...
...
...
...
...
257
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