MC9S12XEP100CAG Freescale Semiconductor, MC9S12XEP100CAG Datasheet - Page 600
![IC MCU 16BIT 1M FLASH 144-LQFP](/photos/12/21/122161/mc9s12xep100cag_sml.jpg)
MC9S12XEP100CAG
Manufacturer Part Number
MC9S12XEP100CAG
Description
IC MCU 16BIT 1M FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEP100CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
119
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
24-ch x 12-bit
Cpu Family
HCS12X
Device Core Size
16b
Frequency (max)
50MHz
Total Internal Ram Size
64KB
# I/os (max)
119
Number Of Timers - General Purpose
25
Operating Supply Voltage (typ)
1.8/2.8/5V
Operating Supply Voltage (max)
1.98/2.9/5.5V
Operating Supply Voltage (min)
1.72/2.7/3.13V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Package
144LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XEP100CAG
Manufacturer:
FREESCAL
Quantity:
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Part Number:
MC9S12XEP100CAG
Manufacturer:
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Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
transfer. In the broadcast, slaves always act as receivers. In general call, IAAS is also used to indicate the
address match.
In order to distinguish whether the address match is the normal address match or the general call address
match, IBDR should be read after the address byte has been received. If the data is $00, the match is
general call address match. The meaning of the general call address is always specified in the first data byte
and must be dealt with by S/W, the IIC hardware does not decode and process the first data byte.
When one byte transfer is done, the received data can be read from IBDR. The user can control the
procedure by enabling or disabling GCEN.
15.4.2
This is the basic mode of operation.
15.4.3
IIC operation in wait mode can be configured. Depending on the state of internal bits, the IIC can operate
normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module
enters a power conservation state during wait mode. In the later case, any transmission or reception in
progress stops at wait mode entry.
15.4.4
The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC
register states.
15.5
The reset state of each individual bit is listed in
which details the registers and their bit-fields.
15.6
IICV3 uses only one interrupt vector.
Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt
type by reading the status register.
IIC Interrupt can be generated on
600
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
1. Arbitration lost condition (IBAL bit set)
Interrupt
Interrupt
Resets
Interrupts
IIC
Operation in Run Mode
Operation in Wait Mode
Operation in Stop Mode
Offset
—
Vector
—
MC9S12XE-Family Reference Manual , Rev. 1.23
Priority
Table 15-12. Interrupt Summary
—
IBAL, TCF, IAAS
bits in IBSR
Section 15.3, “Memory Map and Register
Source
register
When either of IBAL, TCF or IAAS bits is set
may cause an interrupt based on arbitration
lost, transfer complete or address detect
conditions
Description
Freescale Semiconductor
Definition,”
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