MC9S12XEP100CAG Freescale Semiconductor, MC9S12XEP100CAG Datasheet - Page 475

IC MCU 16BIT 1M FLASH 144-LQFP

MC9S12XEP100CAG

Manufacturer Part Number
MC9S12XEP100CAG
Description
IC MCU 16BIT 1M FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
119
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
24-ch x 12-bit
Cpu Family
HCS12X
Device Core Size
16b
Frequency (max)
50MHz
Total Internal Ram Size
64KB
# I/os (max)
119
Number Of Timers - General Purpose
25
Operating Supply Voltage (typ)
1.8/2.8/5V
Operating Supply Voltage (max)
1.98/2.9/5.5V
Operating Supply Voltage (min)
1.72/2.7/3.13V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Package
144LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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11.3.2
This section describes in address order all the S12XECRG registers and their individual bits.
11.3.2.1
The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range.
Read: Anytime
Write: Anytime except if PLLSEL = 1
The VCOFRQ[1:0] bit are used to configure the VCO gain for optimal stability and lock time. For correct
IPLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in
IPLL (no locking and/or insufficient stability).
Freescale Semiconductor
Module Base + 0x0000
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
R
f VCO
f PLL
f BUS
Register Descriptions
=
=
S12XECRG Synthesizer Register (SYNR)
0
=
7
VCOFRQ[1:0]
Write to this register initializes the lock detector bit.
f
Clock) must not exceed the specified maximum. If POSTDIV = $00 then
f
----------------------------------- -
2 POSTDIV
f PLL
------------ -
VCO
PLL
2 f OSC
×
2
×
f VCO
is same as f
must be within the specified VCO frequency lock range. F.
Table
×
0
6
Figure 11-3. S12XECRG Synthesizer Register (SYNR)
(
------------------------------------ -
(
SYNDIV
REFDIV
11-2. Setting the VCOFRQ[1:0] bits wrong can result in a non functional
Table 11-2. VCO Clock Frequency Selection
VCO
MC9S12XE-Family Reference Manual Rev. 1.23
VCOCLK Frequency Ranges
32MHz <= f
80MHz < f
48MHz < f
+
+
(divide by one).
1
1
5
0
)
)
Reserved
VCO
VCO
VCO
<= 80MHz
<= 120MHz
<= 48MHz
NOTE
NOTE
0
4
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
0
3
VCOFRQ[1:0]
SYNDIV[5:0]
00
01
10
11
2
0
BUS
(Bus
0
1
0
0
475

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