MC9S12XEP100CAG Freescale Semiconductor, MC9S12XEP100CAG Datasheet - Page 113
![IC MCU 16BIT 1M FLASH 144-LQFP](/photos/12/21/122161/mc9s12xep100cag_sml.jpg)
MC9S12XEP100CAG
Manufacturer Part Number
MC9S12XEP100CAG
Description
IC MCU 16BIT 1M FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEP100CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
119
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
24-ch x 12-bit
Cpu Family
HCS12X
Device Core Size
16b
Frequency (max)
50MHz
Total Internal Ram Size
64KB
# I/os (max)
119
Number Of Timers - General Purpose
25
Operating Supply Voltage (typ)
1.8/2.8/5V
Operating Supply Voltage (max)
1.98/2.9/5.5V
Operating Supply Voltage (min)
1.72/2.7/3.13V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Package
144LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XEP100CAG
Manufacturer:
FREESCAL
Quantity:
244
Company:
Part Number:
MC9S12XEP100CAG
Manufacturer:
Freescale Semiconductor
Quantity:
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1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
2.3.5
2.3.6
Freescale Semiconductor
Address 0x0002 (PRR)
Address 0x0003 (PRR)
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
DDRA
Field
Field
Reset
Reset
7-0
7-0
PB
W
W
R
R
Port B general purpose input/output data—Data Register
Port B pins 7 through 0 are associated with address outputs ADDR[7:0] respectively in expanded modes. In
emulation modes the address is multiplexed with IVD[7:0]. In normal expanded mode pin 0 is related to the UDS
input.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port A Data Direction—
This register controls the data direction of pins 7 through 0.
The external bus function forces the I/O state to be outputs for all associated pins. In this case the data direction bits
will not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
DDRA7
DDRB7
Port A Data Direction Register (DDRA)
Port B Data Direction Register (DDRB)
0
0
7
7
DDRA6
DDRB6
0
0
6
6
Figure 2-3. Port A Data Direction Register (DDRA)
Figure 2-4. Port B Data Direction Register (DDRB)
Table 2-5. PORTB Register Field Descriptions
Table 2-6. DDRA Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
DDRA5
DDRB5
0
0
5
5
DDRA4
DDRB4
0
0
4
4
Description
Description
DDRA3
DDRB3
3
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
DDRA2
DDRB2
0
0
2
2
Access: User read/write
Access: User read/write
DDRA1
DDRB1
0
0
1
1
DDRA0
DDRB0
0
0
0
0
113
(1)
(1)
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