ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 119

• Manufacturer Part Number: ATXMEGA32A4-CUR
• Description: MCU AVR 32+4 FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA32A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.7
11.7.1
8077H–AVR–12/09
Registers Description
CTRL – Watchdog Timer Control Register
• Bits 7:6 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 5:2 - PER[3:0]: Watchdog Timeout Period
These bits determine the Watchdog timeout period as a number of 1 kHz ULP oscillator cycles.
In window mode operation, these bits define the open window period. The different typical time-
out periods are found in
Timeout Period (WDP) fuses, and will be loaded at power-on.
In order to change these bits the CEN bit must be written to 1 at the same time. These bits are
protected by the Configuration Change Protection mechanism, for detailed description refer to
Section 3.12 ”Configuration Change Protection” on page
Table 11-1.
Bit
+0x00
Read/Write
(unlocked)
Read/Write
(locked)
Initial Value
(x = fuse)
PER[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Watchdog timeout periods
R
R
7
0
-
R
R
6
0
-
Table
Group Configuration
11-1. The initial values of these bits are set by the Watchdog
R/W
R
X
5
125CLK
250CLK
500CLK
1KCLK
2KCLK
4KCLK
8KCLK
16CLK
32CLK
64CLK
8CLK
R/W
R
4
X
PER[3:0]
R/W
R
X
3
12.
R/W
R
2
X
Typical timeout periods
ENABLE
R/W
R
X
1
Reserved
Reserved
Reserved
Reserved
Reserved
0.125 s
16 ms
32 ms
64 ms
0.25 s
8 ms
0.5 s
1.0 s
2.0 s
4.0 s
8.0 s
XMEGA A
CEN
R/W
R
0
0
CTRL
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