ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 251

• Manufacturer Part Number: ATXMEGA32A4-CUR
• Description: MCU AVR 32+4 FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA32A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.15.3
21.15.4
8077H–AVR–12/09
CTRLA – USART Control Register A
CTRLB - USART Control Register B
• Bit 0 - RXB8: Receive Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames with nine
data bits. When used, this bit must be read before reading the low bits from DATA.
This bit unused in Master SPI mode of operation.
• Bit 7:6 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 5:4 - RXCINTLVL[1:0]: Receive Complete Interrupt Level
These bits enable the Receive Complete Interrupt and select the interrupt level as described in
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
enabled interrupt will be triggered when the RXCIF in the STATUS register is set.
• Bit 3:2 - TXCINTLVL[1:0]: Transmit Complete Interrupt Level
These bits enable the Transmit Complete Interrupt and select the interrupt level as described in
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
enabled interrupt will be triggered when the TXCIF in the STATUS register is set.
• Bit 1:0 - DREINTLVL[1:0]: USART Data Register Empty Interrupt Level
These bits enable the Data Register Empty Interrupt and select the interrupt level as described
in
enabled interrupt will be triggered when the DREIF in the STATUS register is set.
• Bit 7:5 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4 - RXEN: Receiver Enable
Setting this bit enables the USART Receiver. The Receiver will override normal port operation
for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the
FERR, BUFOVF, and PERR flags.
Bit
+0x03
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
R
R
7
0
7
0
-
-
R
R
6
0
6
0
-
-
R/W
R
5
RXCINTLVL[1:0]
0
5
0
-
RXEN
R/W
R/W
4
0
4
0
TXEN
R/W
R/W
3
TXCINTLVL[1:0]
0
3
0
CLK2X
R/W
R/W
2
0
2
0
MPCM
R/W
R/W
1
DREINTLVL[1:0]
0
1
0
XMEGA A
TXB8
R/W
R/W
0
0
0
0
123. The
123. The
123. The
CTRLA
CTRLB
251