ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 306

• Manufacturer Part Number: ATXMEGA32A4-CUR
• Description: MCU AVR 32+4 FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA32A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.16.5
25.16.6
8077H–AVR–12/09
PRESCALER - ADC Clock Prescaler register
INTFLAGS - ADC Interrupt Flag register
• Bits 7:3 - Reserved
These bits are reserved and will always read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bits 2:0 - PRESCALER[2:0]: ADC Prescaler configuration
These bits define the ADC clock relative to the Peripheral clock, according to
page
Table 25-7.
• Bits 7:4 - Reserved
These bits are reserved and will always read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bits 3:0 - CH[3:0]IF: Interrupt flags
These flags are set when the ADC conversion is complete for the corresponding ADC channel. If
an ADC channel is configured for compare mode, the corresponding flag will be set if the com-
pare condition is met. CHnIF is automatically cleared when the ADC channel n interrupt vector is
executed. The flag can also be cleared by writing a one to its bit location.
Bit
+0x06
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
PRESCALER[2:0]
306.
000
001
010
011
100
101
110
111
R
R
7
0
7
0
-
-
ADC Prescaler settings
R
6
0
-
R
6
0
-
Group Configuration
R
5
0
-
R
5
0
-
DIV128
DIV256
DIV512
DIV16
DIV32
DIV64
DIV4
DIV8
R
4
0
-
R
4
0
-
R
3
0
-
R/W
3
0
R/W
2
0
R/W
System clock division factor
2
0
CH[3:0]IF
PRESCALER[2:0]
R/W
1
0
R/W
1
0
128
256
512
16
32
64
4
8
XMEGA A
R/W
0
0
R/W
0
0
Table 25-7 on
PRESCALER
INTFLAGS
306