ATMEGA169PV-8AUR Atmel, ATMEGA169PV-8AUR Datasheet - Page 266

• Manufacturer Part Number: ATMEGA169PV-8AUR
• Description: MCU AVR 16KB FLASH 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169PV-8AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 54
• Interface Type: SPI/USART/USI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.5.4
8018P–AVR–08/10
Scanning the Analog Comparator
Table 25-1
XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.
Table 25-1.
Notes:
The relevant Comparator signals regarding Boundary-scan are shown in
Boundary-scan cell from
nals are described in
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Figure 25-7. Analog Comparator
Enable Signal
EXTCLKEN
OSCON
OSC32EN
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided.
summaries the scan registers for the external clock pin XTAL1, oscillators with
Scan Signals for the Oscillator
ADCEN
ACME
Scanned
Clock Line
EXTCLK (XTAL1)
OSCCK
OSC32CK
Table 25-2 on page
ADC MULTIPLEXER
Figure 25-8 on page 267
REFERENCE
BANDGAP
OUTPUT
ACBG
Clock Option
External Clock
External Crystal
External Ceramic Resonator
Low Freq. External Crystal
267.
(1)(2)(3)
ACD
is attached to each of these signals. The sig-
AC_IDLE
ATmega169P
Scanned Clock Line
ACO
when not Used
Figure
1
0
1
25-7. The
266