ATMEGA169PV-8AUR Atmel, ATMEGA169PV-8AUR Datasheet - Page 271

• Manufacturer Part Number: ATMEGA169PV-8AUR
• Description: MCU AVR 16KB FLASH 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169PV-8AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 54
• Interface Type: SPI/USART/USI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8018P–AVR–08/10
Note:
If the ADC is not to be used during scan, the recommended input values from
page 269
scan. Switch-Cap based differential amplifier requires fast operation and accurate timing which
is difficult to obtain when used in a scan chain. Details concerning operations of the differential
amplifier is therefore not provided.
The AVR ADC is based on the analog circuitry shown in
sive approximation algorithm implemented in the digital logic. When used in Boundary-scan, the
problem is usually to ensure that an applied analog voltage is measured within some limits. This
can easily be done without running a successive approximation algorithm: apply the lower limit
on the digital DAC[9:0] lines, make sure the output from the comparator is low, then apply the
upper limit on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following:
• The port pin for the ADC channel in use must be configured to be an input with pull-up disabled
• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low
As an example, consider the task of verifying a 1.5V ±5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
The recommended values from
in the algorithm in
are shown. The column “Actions” describes what JTAG instruction to be used before filling the
Boundary-scan Register with the succeeding columns. The verification should be done on the
data scanned out when scanning in the data on the same row in the table.
to avoid signal contention.
enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
(Sample mode).
1. Incorrect setting of the switches in
should be used. The user is recommended not to use the Differential Amplifier during
may damage the part. There are several input choices to the S&H circuitry on the negative
input of the output comparator in
selected from either one ADC pin, Bandgap reference source, or Ground.
The lower limit is:
The upper limit is:
Table 25-4 on page
Table 25-3 on page 269
1024 1.5V 0,95 5V
1024 1.5V 1.05 5V
272. Only the DAC and port pin values of the Scan Chain
Figure 25-9 on page
Figure 25-9 on page 268
⋅
⋅
⋅
⋅
⁄
⁄
Figure 25-9 on page 268
are used unless other values are given
=
=
268. Make sure only one path is
291
323
CC
=
=
will make signal contention and
.
0x123
0x143
ATmega169P
Table 25-3 on
with a succes-
271