ATMEGA169PV-8AUR Atmel, ATMEGA169PV-8AUR Datasheet - Page 55
ATMEGA169PV-8AUR
Manufacturer Part Number
ATMEGA169PV-8AUR
Description
MCU AVR 16KB FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA169PV-8AU.pdf
(395 pages)
Specifications of ATMEGA169PV-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
54
Interface Type
SPI/USART/USI
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8018P–AVR–08/10
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above.
Timer” on page 52.
• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in
Table 10-2.
Note:
The following code example shows one assembly and one C function for turning off the WDT.
The example assumes that interrupts are controlled (for example by disabling interrupts globally)
so that no interrupts will occur during execution of these functions.
WDP2
to WDE even though it is set to one before the disable operation starts.
0
0
0
0
1
1
1
1
Also see
WDP1
Table
0
0
1
1
0
0
1
1
Watchdog Timer Prescale Select
Figure 29-54 on page
See ”Timed Sequences for Changing the Configuration of the Watchdog
10-2.
WDP0
0
1
0
1
0
1
0
1
Oscillator Cycles
Number of WDT
1,024K cycles
2,048K cycles
128K cycles
256K cycles
512K cycles
16K cycles
32K cycles
64K cycles
366.
Typical Time-out at
V
CC
15.4 ms
30.8 ms
61.6 ms
0.12 s
0.25 s
0.49 s
1.0 s
2.0 s
= 3.0V
ATmega169P
Typical Time-out at
V
CC
14.7 ms
29.3 ms
58.7 ms
0.12 s
0.23 s
0.47 s
0.9 s
1.9 s
= 5.0V
55
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