ATMEGA169PV-8AUR Atmel, ATMEGA169PV-8AUR Datasheet - Page 392

• Manufacturer Part Number: ATMEGA169PV-8AUR
• Description: MCU AVR 16KB FLASH 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169PV-8AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 54
• Interface Type: SPI/USART/USI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8018O–AVR–10/09
23 LCD Controller ..................................................................................... 234
24 JTAG Interface and On-chip Debug System ..................................... 252
25 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 259
26 Boot Loader Support – Read-While-Write Self-Programming ......... 280
22.6Changing Channel or Reference Selection .........................................................221
22.7ADC Noise Canceler ...........................................................................................222
22.8ADC Conversion Result ......................................................................................227
22.9ADC Register Description ...................................................................................229
23.1Features ..............................................................................................................234
23.2Overview .............................................................................................................234
23.3Mode of Operation ...............................................................................................237
23.4LCD Usage ..........................................................................................................242
23.5LCD Register Description ....................................................................................246
24.1Overview .............................................................................................................252
24.2TAP – Test Access Port ......................................................................................253
24.3TAP Controller .....................................................................................................255
24.4Using the Boundary-scan Chain ..........................................................................256
24.5Using the On-chip Debug System .......................................................................256
24.6On-chip Debug Specific JTAG Instructions .........................................................257
24.7On-chip Debug Related Register in I/O Memory .................................................258
24.8Using the JTAG Programming Capabilities .........................................................258
24.9Bibliography .........................................................................................................258
25.1Features ..............................................................................................................259
25.2System Overview ................................................................................................259
25.3Data Registers .....................................................................................................260
25.4Boundary-scan Specific JTAG Instructions .........................................................261
25.5Boundary-scan Chain ..........................................................................................262
25.6Boundary-scan Order ..........................................................................................272
25.7Boundary-scan Description Language Files ........................................................278
25.8Boundary-scan Related Register in I/O Memory .................................................279
26.1Features ..............................................................................................................280
26.2Overview .............................................................................................................280
26.3Application and Boot Loader Flash Sections .......................................................280
26.4Read-While-Write and No Read-While-Write Flash Sections ..............................281
26.5Boot Loader Lock Bits .........................................................................................284
ATmega169P
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