DSPIC30F4013-20E/PT Microchip Technology, DSPIC30F4013-20E/PT Datasheet - Page 151

• Manufacturer Part Number: DSPIC30F4013-20E/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Core Frequency: 20MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401320EPT

20.5
20.5.1
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software mal-
function. The WDT is a free-running timer that runs off
an on-chip RC oscillator, requiring no external compo-
nent. Therefore, the WDT timer continues to operate
even if the main processor clock (e.g., the crystal
oscillator) fails.
20.5.2
The Watchdog Timer can be “Enabled” or “Disabled”
only through a Configuration bit (FWDTEN) in the
Configuration register, FWDT.
Setting FWDTEN = 1 enables the Watchdog Timer. The
enabling is done when programming the device. By
default, after chip erase, FWDTEN bit = 1. Any device
programmer capable of programming dsPIC30F
devices allows programming of this and other
Configuration bits.
If enabled, the WDT increments until it overflows or
“times out”. A WDT time-out forces a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a CLRWDT
instruction.
If a WDT times out during Sleep, the device wakes up.
The WDTO bit in the RCON register is cleared to indi-
cate a wake-up resulting from a WDT time-out.
Setting FWDTEN = 0 allows user software to enable/
disable the Watchdog Timer via the SWDTEN
(RCON<5>) control bit.
20.6
The Low-Voltage Detect (LVD) module is used to
detect when the V
threshold value, V
LVDL<3:0> bits (RCON<11:8>) and is thus user pro-
grammable. The internal voltage reference circuitry
requires a nominal amount of time to stabilize, and the
BGST bit (RCON<13>) indicates when the voltage ref-
erence has stabilized.
In some devices, the LVD threshold voltage may be
applied externally on the LVDIN pin.
The LVD module is enabled by setting the LVDEN bit
(RCON<12>).
© 2007 Microchip Technology Inc.
Watchdog Timer (WDT)
Low-Voltage Detect
WATCHDOG TIMER OPERATION
ENABLING AND DISABLING
THE WDT
LVD
DD
, which is determined by the
of the device drops below a
20.7
There are two power-saving states that can be entered
through the execution of a special instruction, PWRSAV;
these are Sleep and Idle.
The format of the PWRSAV instruction is as follows:
PWRSAV <parameter>, where ‘parameter’ defines
Idle or Sleep mode.
20.7.1
In Sleep mode, the clock to the CPU and peripherals is
shut down. If an on-chip oscillator is being used, it is
shut down.
The Fail-Safe Clock Monitor is not functional during
Sleep since there is no clock to monitor. However,
LPRC clock remains active if WDT is operational during
Sleep.
The brown-out protection circuit and the Low-Voltage
Detect circuit, if enabled, remains functional during
Sleep.
The processor wakes up from Sleep if at least one of
the following conditions has occurred:
• any interrupt that is individually enabled and
• any Reset (POR, BOR and MCLR)
• WDT time-out
On waking up from Sleep mode, the processor restarts
the same clock that was active prior to entry into Sleep
mode. When clock switching is enabled, bits
COSC<2:0> determine the oscillator source to be used
on wake-up. If clock switch is disabled, then there is
only one system clock.
If the clock source is an oscillator, the clock to the
device is held off until OST times out (indicating a sta-
ble oscillator). If PLL is used, the system clock is held
off until LOCK = 1 (indicating that the PLL is stable). In
either case, T
applied.
If EC, FRC, LPRC or ERC oscillators are used, then a
delay of T
delay possible on wake-up from Sleep.
Moreover, if LP oscillator was active during Sleep and
LP is the oscillator used on wake-up, then the start-up
delay is equal to T
delay are not applied. In order to have the smallest
possible start-up delay when waking up from Sleep,
one of these faster wake-up options should be selected
before entering Sleep.
meets the required priority level
Note:
dsPIC30F3014/4013
Power-Saving Modes
POR
SLEEP MODE
If a POR or BOR occurred, the selection of
the oscillator is based on the FOS<2:0>
and FPR<4:0> Configuration bits.
(~ 10 μs) is applied. This is the smallest
POR
, T
POR
LOCK
. PWRT delay and OST timer
and T
DS70138E-page 149
PWRT
delays are