DSPIC30F4013-20E/PT Microchip Technology, DSPIC30F4013-20E/PT Datasheet - Page 212

IC DSPIC MCU/DSP 48K 44TQFP

DSPIC30F4013-20E/PT

Manufacturer Part Number
DSPIC30F4013-20E/PT
Description
IC DSPIC MCU/DSP 48K 44TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F4013-20E/PT

Program Memory Type
FLASH
Program Memory Size
48KB (16K x 24)
Package / Case
44-TQFP, 44-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
Number Of I /o
30
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
30
Data Ram Size
2 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Package
44TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
13-chx12-bit
Number Of Timers
5
Core Frequency
20MHz
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
48KB
Supply Voltage Range
2.5V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F401320EPT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F4013-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F3014/4013
D
Data Accumulators and Adder/Subtracter........................... 19
Data Accumulators and Adder/Subtractor
Data Address Space ........................................................... 28
Data Converter Interface (DCI) Module ............................ 115
Data EEPROM Memory ...................................................... 47
DC Characteristics ............................................................ 165
DCI Module
DS70138E-page 210
Data Space Write Saturation ...................................... 21
Overflow and Saturation ............................................. 19
Round Logic ................................................................ 20
Write-Back .................................................................. 20
Alignment .................................................................... 31
Alignment (Figure) ...................................................... 31
Effect of Invalid Memory Accesses (Table)................. 31
MCU and DSP (MAC Class) Instructions Example..... 30
Memory Map ......................................................... 28, 29
Near Data Space ........................................................ 32
Software Stack ............................................................ 32
Spaces ........................................................................ 31
Width ........................................................................... 31
Erasing ........................................................................ 48
Erasing, Block ............................................................. 48
Erasing, Word ............................................................. 48
Protection Against Spurious Write .............................. 50
Reading....................................................................... 47
Write Verify ................................................................. 50
Writing ......................................................................... 49
Writing, Block .............................................................. 49
Writing, Word .............................................................. 49
BOR .......................................................................... 173
Brown-out Reset ....................................................... 172
I/O Pin Input Specifications ....................................... 171
I/O Pin Output Specifications .................................... 171
Idle Current (I
Low-Voltage Detect................................................... 171
LVDL ......................................................................... 172
Operating Current (I
Power-Down Current (I
Program and EEPROM............................................. 173
Temperature and Voltage Specifications .................. 165
Bit Clock Generator................................................... 119
Buffer Alignment with Data Frames .......................... 121
Buffer Control ............................................................ 115
Buffer Data Alignment ............................................... 115
Buffer Length Control ................................................ 121
COFS Pin .................................................................. 115
CSCK Pin .................................................................. 115
CSDI Pin ................................................................... 115
CSDO Mode Bit ........................................................ 122
CSDO Pin ................................................................. 115
Data Justification Control Bit ..................................... 120
Device Frequencies for Common Codec
Digital Loopback Mode ............................................. 122
Enable ....................................................................... 117
Frame Sync Generator ............................................. 117
Frame Sync Mode Control Bits ................................. 117
I/O Pins ..................................................................... 115
Interrupts ................................................................... 122
Introduction ............................................................... 115
Master Frame Sync Operation .................................. 117
Operation .................................................................. 117
Operation During CPU Idle Mode ............................. 122
Operation During CPU Sleep Mode .......................... 122
CSCK Frequencies (Table)............................... 119
IDLE
) .................................................... 168
DD
)............................................. 167
PD
) ........................................ 169
Development Support ....................................................... 161
Device Configuration
Device Configuration Registers
Device Overview................................................................... 9
Disabling the UART ............................................................ 99
Divide Support .................................................................... 16
DSP Engine ........................................................................ 17
Dual Output Compare Match Mode .................................... 82
E
Electrical Characteristics .................................................. 165
Enabling and Setting Up UART
Enabling the UART ............................................................. 99
Equations
Errata .................................................................................... 7
Exception Sequence
External Clock Timing Characteristics
External Clock Timing Requirements ............................... 175
External Interrupt Requests ................................................ 60
F
Fast Context Saving ........................................................... 60
Flash Program Memory ...................................................... 41
Receive Slot Enable Bits .......................................... 120
Receive Status Bits................................................... 121
Register Map ............................................................ 124
Sample Clock Edge Control Bit ................................ 120
Slave Frame Sync Operation.................................... 118
Slot Enable Bits Operation with Frame Sync............ 120
Slot Status Bits ......................................................... 122
Synchronous Data Transfers .................................... 120
Timing Characteristics
Timing Requirements
Transmit Slot Enable Bits ......................................... 120
Transmit Status Bits.................................................. 121
Transmit/Receive Shift Register ............................... 115
Underflow Mode Control Bit...................................... 122
Word Size Selection Bits .......................................... 117
Register Map ............................................................ 152
FBORPOR ................................................................ 150
FGS .......................................................................... 150
FOSC........................................................................ 150
FWDT ....................................................................... 150
Instructions (Table) ..................................................... 16
Multiplier ..................................................................... 19
Continuous Pulse Mode.............................................. 82
Single Pulse Mode...................................................... 82
AC............................................................................. 174
DC ............................................................................ 165
Alternate I/O ............................................................... 99
Setting Up Data, Parity and Stop Bit Selections ......... 99
ADC Conversion Clock ............................................. 127
Baud Rate................................................................. 101
Bit Clock Frequency.................................................. 119
COFSG Period.......................................................... 117
Serial Clock Rate ........................................................ 90
Time Quantum for Clock Generation ........................ 111
Trap Sources .............................................................. 58
Type A, B and C Timer ............................................. 181
Type A Timer ............................................................ 181
Type B Timer ............................................................ 182
Type C Timer ............................................................ 182
AC-Link Mode................................................... 187
Multichannel, I
AC-Link Mode................................................... 188
Multichannel, I
2
2
S Modes................................... 185
S Modes................................... 185
© 2007 Microchip Technology Inc.

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