DSPIC30F4013-20E/PT Microchip Technology, DSPIC30F4013-20E/PT Datasheet - Page 51

• Manufacturer Part Number: DSPIC30F4013-20E/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Core Frequency: 20MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401320EPT

6.3
To write an EEPROM data location, the following
sequence must be followed:
1.
2.
3.
EXAMPLE 6-4:
© 2007 Microchip Technology Inc.
; Point to data memory
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
; Operate key to allow write operation
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
Erase data EEPROM word.
a)
b)
c)
d)
e)
f)
g)
h)
Write data word into data EEPROM write
latches.
Program 1 data word into data EEPROM.
a)
b)
c)
d)
e)
f)
g)
MOV
MOV
MOV
MOV
TBLWTL
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
Writing to the Data EEPROM
Select word, data EEPROM erase, and set
WREN bit in NVMCON register.
Write address of word to be erased into
NVMADR.
Enable NVM interrupt (optional).
Write ‘55’ to NVMKEY.
Write ‘AA’ to NVMKEY.
Set the WR bit. This begins erase cycle.
Either poll NVMIF bit or wait for NVMIF
interrupt.
The WR bit is cleared when the erase cycle
ends.
Select word, data EEPROM program, and
set WREN bit in NVMCON register.
Enable NVM write done interrupt (optional).
Write ‘55’ to NVMKEY.
Write ‘AA’ to NVMKEY.
Set the WR bit. This begins program cycle.
Either poll NVMIF bit or wait for NVM
interrupt.
The WR bit is cleared when the write cycle
ends.
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1
#LOW(WORD),W2
W2
#0x4004,W0
W0
#5
#0x55,W0
W0
#0xAA,W1
W1
NVMCON,#WR
,
,
,
,
,
DATA EEPROM WORD WRITE
TBLPAG
[ W0]
NVMCON
NVMKEY
NVMKEY
; Init pointer
; Get data
; Write data
; Block all interrupts with priority <7 for
; next 5 instructions
; Write the 0x55 key
; Write the 0xAA key
; Initiate program sequence
The write does not initiate if the above sequence is not
exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution. The WREN bit should be kept clear at all times
except when updating the EEPROM. The WREN bit is
not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit does not affect the current write cycle. The
WR bit is inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the Nonvolatile Memory Write
Complete Interrupt Flag bit (NVMIF) is set. The user
may either enable this interrupt or poll this bit. NVMIF
must be cleared by software.
6.3.1
Once the user has erased the word to be programmed,
then a table write instruction is used to write one write
latch, as shown in Example 6-4.
6.3.2
To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and
program the block, as shown in Example 6-5.
dsPIC30F3014/4013
WRITING A WORD OF DATA
EEPROM
WRITING A BLOCK OF DATA
EEPROM
DS70138E-page 49