AT89C5131A-PUTUM Atmel, AT89C5131A-PUTUM Datasheet - Page 124

• Manufacturer Part Number: AT89C5131A-PUTUM
• Description: IC 8051 MCU FLASH 32K USB 32QFN
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-PUTUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 48 MHz
• Data Ram Size: 1.25 KB
• Number Of Programmable I/os: 34
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 5.5 V
• Mounting Style: SMD/SMT
• Height: 0.95 mm
• Interface Type: 2-Wire, EUART, SPI, USB
• Length: 7 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

21.3
21.3.1
124
Read/Write Data FIFO
AT89C5130A/31A-M
FIFO Mapping
Table 21-1.
Depending on the selected endpoint through the UEPNUM register, the UEPDATX register
allows to access the corresponding endpoint data fifo.
Endpoint Configuration
Disabled
Control
Bulk-in
Bulk-out
Interrupt-In
Interrupt-Out
Isochronous-In
Isochronous-Out
• Endpoint direction configuration
• Summary of Endpoint Configuration:
• Endpoint FIFO reset
The Endpoint 0 is the Default Control Endpoint and will always be configured in Control type.
For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of
the UEPCONX register with the following values:
For Control endpoints, the EPDIR bit has no effect.
Do not forget to select the correct endpoint number in the UEPNUM register before access-
ing to endpoint specific registers.
Before using an endpoint, its FIFO will be reset. This action resets the FIFO pointer to its
original value, resets the byte counter of the endpoint (UBYCTLX and UBYCTHX registers),
and resets the data toggle bit (DTGL bit in UEPCONX).
The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the corre-
sponding bit in the UEPRST register.
For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000
0000b in the UEPRST register.
Note that the endpoint reset doesn’t reset the bank number for ping-pong endpoints.
– IN:EPDIR = 1b
– OUT:EPDIR = 0b
Summary of Endpoint Configuration
EPEN
0b
1b
1b
1b
1b
1b
1b
1b
EPDIR
Xb
Xb
1b
0b
1b
0b
1b
0b
EPTYPE
XXb
00b
10b
10b
01b
01b
11b
11b
0XXX XXXb
UEPCONX
4337K–USB–04/08
80h
86h
82h
87h
83h
85h
81h