AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet - Page 128

• Manufacturer Part Number: AT91SAM7S321-AU
• Description: IC ARM7 MCU FLASH 32K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S321-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, I2S, SPI, SSC, TWI, UART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 10 bit
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 32
• Ram Memory Size: 8KB
• Cpu Speed: 55MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 20-4. AT91SAM7S32/16 Parallel Programming Timing, Write Sequence
Table 20-4.
20.2.4.2
Figure 20-5.
128
Step
1
2
3
4
5
6
AT91SAM7S Series Preliminary
Programmer Action
Sets MODE and DATA signals
Clears NCMD signal
Waits for RDY low
Releases MODE and DATA signals
Sets NCMD signal
Waits for RDY high
Read Handshaking
Write Handshake
AT91SAM7S542/256/128/321/161 Parallel Programming Timing, Read Sequence
DATA[15:0]
MODE[3:0]
MODE[3:0]
DATA[7:0]
For details on the read handshaking sequence, refer to
NVALID
NVALID
NCMD
NCMD
NOE
NOE
RDY
RDY
1
1
2
2
Adress IN
ADDR
3
3
Waits for NCMD low
Latches MODE and DATA
Clears RDY signal
Executes command and polls NCMD high
Executes command and polls NCMD high
Sets RDY
Device Action
4
5
Z
4
6
7
Data OUT
5
8
9
Figure
10
11
X
12
20-5,
13
IN
Figure 20-6
Data I/O
Input
Input
Input
Input
Input
Input
6175K–ATARM–30-Aug-10
and
Table
20-5.