AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet - Page 98

IC ARM7 MCU FLASH 32K 64LQFP

AT91SAM7S321-AU

Manufacturer Part Number
AT91SAM7S321-AU
Description
IC ARM7 MCU FLASH 32K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM7S321-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, I2S, SPI, SSC, TWI, UART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
32
Number Of Timers
10 bit
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxx
No. Of I/o's
32
Ram Memory Size
8KB
Cpu Speed
55MHz
No. Of Timers
3
Rohs Compliant
Yes
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S321-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7S321-AU-999
Manufacturer:
Atmel
Quantity:
10 000
18.3
18.3.1
18.3.2
98
Functional Description
AT91SAM7S Series Preliminary
Bus Arbiter
Address Decoder
The Memory Controller handles the internal ASB bus and arbitrates the accesses of both
masters.
It is made up of:
The MC handles only little-endian mode accesses. The masters work in little-endian mode only.
The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the
bus to one of the two masters. The Peripheral DMA Controller has the highest priority; the ARM
processor has the lowest one.
The Memory Controller features an Address Decoder that first decodes the four highest bits of
the 32-bit address bus and defines three separate areas:
Figure 18-2
Figure 18-2. Memory Areas
• A bus arbiter
• An address decoder
• An abort status
• A misalignment detector
• An Embedded Flash Controller
• One 256-Mbyte address space for the internal memories
• One 256-Mbyte address space reserved for the embedded peripherals
• An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that
return an Abort if accessed
shows the assignment of the 256-Mbyte memory areas.
14 x 256MBytes
256M Bytes
256M Bytes
3,584 Mbytes
0xF000 0000
0x0000 0000
0xEFFF FFFF
0xFFFF FFFF
0x0FFF FFFF
0x1000 0000
Internal Memories
Peripherals
Undefined
(Abort)
6175K–ATARM–30-Aug-10

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