AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet - Page 131

• Manufacturer Part Number: AT91SAM7S321-AU
• Description: IC ARM7 MCU FLASH 32K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S321-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, I2S, SPI, SSC, TWI, UART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 10 bit
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 32
• Ram Memory Size: 8KB
• Cpu Speed: 55MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.2.5.2
6175K–ATARM–30-Aug-10
Flash Write Command
Table 20-7.
This command is used to write the Flash contents.
The Flash memory plane is organized into several pages. Data to be written are stored in a load
buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the
Flash:
The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be
chained; an internal address buffer is automatically increased.
Table 20-8.
Table 20-9.
Step
n+1
n+2
n+3
n+4
n+5
...
Step
1
2
3
4
5
...
n
n+1
n+2
n+3
...
Step
1
2
3
4
• before access to any page other than the current one
• when a new command is validated (MODE = CMDE)
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Read handshaking
Read handshaking
...
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
...
Write handshaking
Write handshaking
Write handshaking
Write handshaking
...
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Read Command (Continued)
Write Command
Write Command
AT91SAM7S Series Preliminary
ADDR1
...
ADDR1
DATA
DATA
...
MODE[3:0]
CMDE
ADDR0
ADDR1
ADDR2
MODE[3:0]
CMDE
ADDR0
DATA
DATA
ADDR0
MODE[3:0]
ADDR1
ADDR2
ADDR3
DATA
DATA
...
DATA[7:0]
Memory Address LSB
Memory Address
Memory Address
DATA[15:0]
WP or WPL or EWP or EWPL
Memory Address LSB
Memory Address
*Memory Address++
*Memory Address++
...
Memory Address LSB
Memory Address
*Memory Address++
*Memory Address++
...
WP or WPL or EWP or EWPL
Memory Address
Memory Address
Memory Address
*Memory Address++
*Memory Address++
...
DATA[7:0]
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