AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet - Page 418

IC ARM7 MCU FLASH 32K 64LQFP

AT91SAM7S321-AU

Manufacturer Part Number
AT91SAM7S321-AU
Description
IC ARM7 MCU FLASH 32K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM7S321-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, I2S, SPI, SSC, TWI, UART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
32
Number Of Timers
10 bit
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxx
No. Of I/o's
32
Ram Memory Size
8KB
Cpu Speed
55MHz
No. Of Timers
3
Rohs Compliant
Yes
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S321-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7S321-AU-999
Manufacturer:
Atmel
Quantity:
10 000
32.6.8
32.6.9
418
AT91SAM7S Series Preliminary
Loop Mode
Interrupt
Note:
Figure 32-15. Receive Frame Format in Continuous Mode
Note:
The receiver can be programmed to receive transmissions from the transmitter. This is done by
setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is
connected to TF and RK is connected to TK.
Most bits in SSC_SR have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is
controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Reg-
ister) These registers enable and disable, respectively, the corresponding interrupt by setting
and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the
generation of interrupts by asserting the SSC interrupt line connected to the AIC.
Figure 32-16. Interrupt Block Diagram
1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on
1. STTDLY is set to 0.
the transmission. SyncData cannot be output in continuous mode.
TXBUFE
ENDTX
RXBUFF
ENDRX
PDC
RD
Transmitter
Receiver
Start = Enable Receiver
TXEMPTY
TXSYNC
RXSYNC
OVRUN
To SSC_RHR
TXRDY
RXRDY
DATLEN
Data
SSC_IER
To SSC_RHR
Set
DATLEN
SSC_IMR
Data
Interrupt
Control
SSC_IDR
Clear
SSC Interrupt
6175K–ATARM–30-Aug-10

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