AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet - Page 768
![IC ARM7 MCU FLASH 32K 64LQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT91SAM7S321-AU
Manufacturer Part Number
AT91SAM7S321-AU
Description
IC ARM7 MCU FLASH 32K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91SAM7S16-MU.pdf
(51 pages)
2.AT91SAM7S16-MU.pdf
(779 pages)
3.AT91SAM7S321-AU.pdf
(600 pages)
Specifications of AT91SAM7S321-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, I2S, SPI, SSC, TWI, UART, USB
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
32
Number Of Timers
10 bit
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AT91SAM7xxxx
No. Of I/o's
32
Ram Memory Size
8KB
Cpu Speed
55MHz
No. Of Timers
3
Rohs Compliant
Yes
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 768 of 779
- Download datasheet (11Mb)
758
Version
6175C
AT91SAM7S Series Preliminary
Comments
AT91SAM7S321 addresses
Values given in PIO Line column:
Section 40. ”Errata”
Section 40.6.3.1 ”MCK: Limited Master Clock Frequency Ranges”
Section 40.10.3.1 ”MCK: Limited Master Clock Frequency Ranges”
Section 40.14.3.1 ”MCK: Limited Master Clock Frequency Ranges”
Section 40.19.3.1 ”MCK: Limited Master Clock Frequency Ranges”
and
Section 40.6.4.1 ”NVM Bits: Write/Erase Cycles Number”
Section 40.10.4.1 ”NVM Bits: Write/Erase Cycles Number”
Section 40.14.4.1 ”NVM Bits: Write/Erase Cycles Number”
Section 40.19.4.1 ”NVM Bits: Write/Erase Cycles Number”
note
”Voltage Regulator Mode Register” page
AT91SAM7S321 addresses
Values given in PIO Line column:
(2)
added to
Table 37-24, “Embedded Flash Wait States,” on page 578
added lines and note to the following:
redefined:Table 22-4, “User Area Addresses,” on page 171
redefined:Table 22-4, “User Area Addresses,” on page 171
Table 22-5, “Pins Driven during Boot Program Execution,” on page 171
Table 22-5, “Pins Driven during Boot Program Execution,” on page 171
118, bit field name corrected
AT91SAM7S256
AT91SAM7S128
AT91SAM7S64
AT91SAM7S32
AT91SAM7S256
AT91SAM7S128
AT91SAM7S64
AT91SAM7S32
”PSTDBY: Power Standby Mode”
6175K–ATARM–30-Aug-10
Change
Request
Ref
#1217
#1547 and
review
review
#1585
#1217
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