AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet - Page 602

• Manufacturer Part Number: AT91SAM7S321-AU
• Description: IC ARM7 MCU FLASH 32K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S321-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, I2S, SPI, SSC, TWI, UART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 10 bit
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 32
• Ram Memory Size: 8KB
• Cpu Speed: 55MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

40.4.8.4
40.4.8.5
40.4.9
40.4.9.1
40.4.9.2
40.4.9.3
40.4.9.4
602
AT91SAM7S Series Preliminary
Universal Synchronous Asynchronous Receiver Transmitter (USART)
TWI: NACK Status Bit Lost
TWI: Possible Receive Holding Register Corruption
USART: CTS in Hardware Handshaking
USART: Hardware Handshaking – Two Characters Sent
USART: XOFF Character Bad Behavior
USART: RXBRK Flag Error in Asynchronous Mode
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection
and the TXCOMP bit rising in the TWI_SR, the NACK bit is not set.
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as
long as transmission is not completed.
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of
the TWI_SR.
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the
TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor
OVERRUN status bits are set if this occurs.
The user must be sure that received data is read before transmitting any new data.
When Hardware Handshaking is used and if CTS goes high near the end of the start bit, a char-
acter can be lost.
CTS must not go high during a time slot occurring between 2 Master Clock periods before and
16 Master Clock periods after the rising edge of the start bit.
None.
If CTS switches from 0 to 1 during the TX of a character and if the holding register (US_THR) is
not empty, the content of US_THR will also be transmitted.
Don't use the PDC in transmit mode and do not fill US_THR before TXEMPTY is set at 1.
The XOFF character is sent only when the receive buffer is detected full. While the XOFF is
being sent, the remote transmitter is still transmitting. As only one Holding register is available in
the receiver, characters will be lost in reception. This makes the software handshaking function-
ality ineffective.
None.
In receiver mode, when there are two consecutive characters (without timeguard in between),
RXBRK is not taken into account. As a result, the RXBRK flag is not enabled correctly and the
frame error flag is set.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6175K–ATARM–30-Aug-10