AT91SAM7S321-AU Atmel, AT91SAM7S321-AU Datasheet - Page 592

• Manufacturer Part Number: AT91SAM7S321-AU
• Description: IC ARM7 MCU FLASH 32K 64LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S321-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, I2S, SPI, SSC, TWI, UART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 10 bit
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Controller Family/series: AT91SAM7xxxx
• No. Of I/o's: 32
• Ram Memory Size: 8KB
• Cpu Speed: 55MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

40.2
Table 40-1.
592
Part
Chip ID
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
EFC
JTAG
MCK
NVM Bits
PIO
PIO
PIO
PMC
PMC
PWM
PWM
PWM
PWM
Errata Summary by Product and Revision or Manufacturing Number
AT91SAM7S Series Preliminary
Errata
Wrong Chip ID Value
DRDY Bit Cleared
DRDY not Cleared on Disable
DRDY Possibly Skipped due to CDR Read
Possible Skip on DRDY when Disabling a
Channel
GOVRE Bit is not Updated
GOVRE Bit is not Set when Reading CDR
GOVRE Bit is not Set when Disabling a Channel
OVRE Flag Behavior
EOC Set although Channel Disabled
Spurious Clear of EOC Flag
Sleep Mode
Embedded Flash Access Time 1
Embedded Flash Access Time 2
Recommendation for TDI Pin
Limited Master Clock Frequency Ranges
Leakage on PA17 - PA20
Electrical Characteristics on NRST and PA0-
PA16 and PA21-31
Drive Low NRST, PA0-PA16 and PA21-PA31
Slow Clock Selected in PMC and a Transition
Occurs on PA1
Programming CSS in PMC_MCKR Register
Update when PWM_CCNTx = 0 or 1
Update when PWM_CPRDx = 0
Counter Start Value
Constraints on Duty Cycle Value
Write/Erase Cycles Number
Errata Summary Table
Revision or Manufacturing Number
AT91SAM7Sx Product
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6175K–ATARM–30-Aug-10
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